syncreg_r Entity Reference

Inheritance diagram for syncreg_r:

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Generics
size	positive := 32

Ports
m_clk	in std_logic
m_rst	in std_logic
m_re	in std_logic
m_busy	out std_logic
m_ack	out std_logic
m_q	out std_logic_vector ( size - 1 downto 0 )
s_clk	in std_logic
s_d	in std_logic_vector ( size - 1 downto 0 )
s_stb	out std_logic

Member Data Documentation

IEEE

IEEE

Library

m_ack

m_ack out std_logic

Port

m_busy

m_busy out std_logic

Port

m_clk

m_clk in std_logic

Port

m_q

m_q out std_logic_vector ( size - 1 downto 0 )

Port

m_re

m_re in std_logic

Port

m_rst

m_rst in std_logic

Port

s_clk

s_clk in std_logic

Port

s_d

s_d in std_logic_vector ( size - 1 downto 0 )

Port

s_stb

s_stb out std_logic

Port

size

size positive := 32

Generic

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/syncreg_r.vhd