rtl Architecture Reference

Processes
PROCESS_300	( m_clk )
PROCESS_301	( s_clk )
PROCESS_860	( m_clk )
PROCESS_861	( s_clk )

Signals
q	std_logic_vector ( size - 1 downto 0 )
we_v	std_logic
busy	std_logic
ack	std_logic
s1	std_logic
s2	std_logic
s3	std_logic
m1	std_logic
m2	std_logic
m3	std_logic

Attributes
SHREG_EXTRACT	string
SHREG_EXTRACT	s1 : signal is " no "
SHREG_EXTRACT	m1 : signal is " no "

Member Function Documentation

PROCESS_300()

PROCESS_300 (   m_clk   )

Process

PROCESS_301()

PROCESS_301 (   s_clk   )

Process

PROCESS_860()

PROCESS_860 (   m_clk   )

Process

PROCESS_861()

PROCESS_861 (   s_clk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

busy

busy std_logic

Signal

m1

m1 std_logic

Signal

m2

m2 std_logic

Signal

m3

m3 std_logic

Signal

q

q std_logic_vector ( size - 1 downto 0 )

Signal

s1

s1 std_logic

Signal

s2

s2 std_logic

Signal

s3

s3 std_logic

Signal

SHREG_EXTRACT [1/3]

SHREG_EXTRACT string

Attribute

SHREG_EXTRACT [2/3]

SHREG_EXTRACT s1 : signal is " no "

Attribute

SHREG_EXTRACT [3/3]

SHREG_EXTRACT m1 : signal is " no "

Attribute

we_v

we_v std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/syncreg_w.vhd