temac_gbe_v9_0_gmii_gmii_if Entity Reference

Inheritance diagram for temac_gbe_v9_0_gmii_gmii_if:

Entities
PHY_IF	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
tx_reset	in std_logic
rx_reset	in std_logic
gmii_txd	out std_logic_vector ( 7 downto 0 )
gmii_tx_en	out std_logic
gmii_tx_er	out std_logic
gmii_tx_clk	out std_logic
gmii_rxd	in std_logic_vector ( 7 downto 0 )
gmii_rx_dv	in std_logic
gmii_rx_er	in std_logic
gmii_rx_clk	in std_logic
txd_from_mac	in std_logic_vector ( 7 downto 0 )
tx_en_from_mac	in std_logic
tx_er_from_mac	in std_logic
tx_clk	in std_logic
rxd_to_mac	out std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rx_dv_to_mac	out std_logic := ' 0 '
rx_er_to_mac	out std_logic := ' 0 '
rx_clk	out std_logic

Member Data Documentation

gmii_rx_clk

gmii_rx_clk in std_logic

Port

gmii_rx_dv

gmii_rx_dv in std_logic

Port

gmii_rx_er

gmii_rx_er in std_logic

Port

gmii_rxd

gmii_rxd in std_logic_vector ( 7 downto 0 )

Port

gmii_tx_clk

gmii_tx_clk out std_logic

Port

gmii_tx_en

gmii_tx_en out std_logic

Port

gmii_tx_er

gmii_tx_er out std_logic

Port

gmii_txd

gmii_txd out std_logic_vector ( 7 downto 0 )

Port

ieee

ieee

Library

rx_clk

rx_clk out std_logic

Port

rx_dv_to_mac

rx_dv_to_mac out std_logic := ' 0 '

Port

rx_er_to_mac

rx_er_to_mac out std_logic := ' 0 '

Port

rx_reset

rx_reset in std_logic

Port

rxd_to_mac

rxd_to_mac out std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Port

std_logic_1164

std_logic_1164

Package

tx_clk

tx_clk in std_logic

Port

tx_en_from_mac

tx_en_from_mac in std_logic

Port

tx_er_from_mac

tx_er_from_mac in std_logic

Port

tx_reset

tx_reset in std_logic

Port

txd_from_mac

txd_from_mac in std_logic_vector ( 7 downto 0 )

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/synth/physical/temac_gbe_v9_0_gmii_gmii_if.vhd