top Entity Reference

Inheritance diagram for top:

Collaboration diagram for top:

Entities
rtl	architecture

Libraries
IEEE
ieee

Use Clauses
STD_LOGIC_1164
ipbus	Package <ipbus>
mac_arbiter_decl	Package <mac_arbiter_decl>
ipbus_decode_glib_v3_basex	Package <ipbus_decode_glib_v3_basex>
ipbus_trans_decl	Package <ipbus_trans_decl>
top_decl	Package <top_decl>
std_logic_1164
numeric_std
mp7_data_types
mp7_readout_decl
mp7_ttc_decl

Ports
leds	out std_logic_vector ( 2 downto 0 )
sgmii_clkp	in std_logic
sgmii_clkn	in std_logic
sgmii_txp	out std_logic
sgmii_txn	out std_logic
sgmii_rxp	in std_logic
sgmii_rxn	in std_logic
phy_rstb	out std_logic
gt_clkp	in std_logic
gt_clkn	in std_logic
gt_txp	out std_logic
gt_txn	out std_logic
gt_rxp	in std_logic
gt_rxn	in std_logic
sda	inout std_logic
scl	inout std_logic
v6_cpld	inout std_logic_vector ( 0 to 5 )
eth_clkp	in std_logic
eth_clkn	in std_logic
eth_txp	out std_logic
eth_txn	out std_logic
eth_rxp	in std_logic
eth_rxn	in std_logic
clk_ctrl	out std_logic_vector ( 7 downto 0 )
clk40_in_p	in std_logic
clk40_in_n	in std_logic
ttc_in_p	in std_logic
ttc_in_n	in std_logic
fpga_sda	inout std_logic
fpga_scl	inout std_logic
clk_in_p	in std_logic
clk_in_n	in std_logic
xpoint_ctrl	out std_logic_vector ( 9 downto 0 )
d_p	in std_logic_vector ( N_IN- 1 downto 0 )
d_n	in std_logic_vector ( N_IN- 1 downto 0 )
q_p	out std_logic_vector ( N_OUT- 1 downto 0 )
q_n	out std_logic_vector ( N_OUT- 1 downto 0 )
sysclk	in STD_LOGIC
gmii_gtx_clk	out STD_LOGIC
gmii_tx_en	out STD_LOGIC
gmii_tx_er	out STD_LOGIC
gmii_txd	out STD_LOGIC_VECTOR ( 7 downto 0 )
gmii_rx_clk	in STD_LOGIC
gmii_rx_dv	in STD_LOGIC
gmii_rx_er	in STD_LOGIC
gmii_rxd	in STD_LOGIC_VECTOR ( 7 downto 0 )
dip_switch	in std_logic_vector ( 3 downto 0 )
gt_clk_p	in std_logic
gt_clk_n	in std_logic
gt_tx_p	out std_logic
gt_tx_n	out std_logic
gt_rx_p	in std_logic
gt_rx_n	in std_logic
sfp_los	in std_logic
sysclk_p	in STD_LOGIC
sysclk_n	in STD_LOGIC
gtp_clkp	in std_logic
gtp_clkn	in std_logic
gtp_txp	out std_logic
gtp_txn	out std_logic
gtp_rxp	in std_logic
gtp_rxn	in std_logic
sys_clk_pin	in STD_LOGIC
gmii_tx_clk	out STD_LOGIC
leds_gpoi	out std_logic_vector ( 7 downto 0 )
refclkp	in std_logic_vector ( N_REFCLK - 1 downto 0 )
refclkn	in std_logic_vector ( N_REFCLK - 1 downto 0 )
eth_clk_p	in std_logic
eth_clk_n	in std_logic
eth_rx_p	in std_logic
eth_rx_n	in std_logic
eth_tx_p	out std_logic
eth_tx_n	out std_logic
flash_csn	out STD_LOGIC
flash_mosi	out STD_LOGIC
flash_miso	in STD_LOGIC
flash_led	out STD_LOGIC
phy_rst	out std_logic

Member Data Documentation

clk40_in_n

clk40_in_n in std_logic

Port

clk40_in_p

clk40_in_p in std_logic

Port

clk_ctrl

clk_ctrl out std_logic_vector ( 7 downto 0 )

Port

clk_in_n

clk_in_n in std_logic

Port

clk_in_p

clk_in_p in std_logic

Port

d_n

d_n in std_logic_vector ( N_IN- 1 downto 0 )

Port

d_p

d_p in std_logic_vector ( N_IN- 1 downto 0 )

Port

dip_switch

dip_switch in std_logic_vector ( 3 downto 0 )

Port

eth_clk_n

eth_clk_n in std_logic

Port

eth_clk_p

eth_clk_p in std_logic

Port

eth_clkn

eth_clkn in std_logic

Port

eth_clkp

eth_clkp in std_logic

Port

eth_rx_n

eth_rx_n in std_logic

Port

eth_rx_p

eth_rx_p in std_logic

Port

eth_rxn

eth_rxn in std_logic

Port

eth_rxp

eth_rxp in std_logic

Port

eth_tx_n

eth_tx_n out std_logic

Port

eth_tx_p

eth_tx_p out std_logic

Port

eth_txn

eth_txn out std_logic

Port

eth_txp

eth_txp out std_logic

Port

flash_csn

flash_csn out STD_LOGIC

Port

flash_led

flash_led out STD_LOGIC

Port

flash_miso

flash_miso in STD_LOGIC

Port

flash_mosi

flash_mosi out STD_LOGIC

Port

fpga_scl

fpga_scl inout std_logic

Port

fpga_sda

fpga_sda inout std_logic

Port

gmii_gtx_clk

gmii_gtx_clk out STD_LOGIC

Port

gmii_rx_clk

gmii_rx_clk in STD_LOGIC

Port

gmii_rx_dv

gmii_rx_dv in STD_LOGIC

Port

gmii_rx_er

gmii_rx_er in STD_LOGIC

Port

gmii_rxd

gmii_rxd in STD_LOGIC_VECTOR ( 7 downto 0 )

Port

gmii_tx_clk

gmii_tx_clk out STD_LOGIC

Port

gmii_tx_en

gmii_tx_en out STD_LOGIC

Port

gmii_tx_er

gmii_tx_er out STD_LOGIC

Port

gmii_txd

gmii_txd out STD_LOGIC_VECTOR ( 7 downto 0 )

Port

gt_clk_n

gt_clk_n in std_logic

Port

gt_clk_p

gt_clk_p in std_logic

Port

gt_clkn

gt_clkn in std_logic

Port

gt_clkp

gt_clkp in std_logic

Port

gt_rx_n

gt_rx_n in std_logic

Port

gt_rx_p

gt_rx_p in std_logic

Port

gt_rxn

gt_rxn in std_logic

Port

gt_rxp

gt_rxp in std_logic

Port

gt_tx_n

gt_tx_n out std_logic

Port

gt_tx_p

gt_tx_p out std_logic

Port

gt_txn

gt_txn out std_logic

Port

gt_txp

gt_txp out std_logic

Port

gtp_clkn

gtp_clkn in std_logic

Port

gtp_clkp

gtp_clkp in std_logic

Port

gtp_rxn

gtp_rxn in std_logic

Port

gtp_rxp

gtp_rxp in std_logic

Port

gtp_txn

gtp_txn out std_logic

Port

gtp_txp

gtp_txp out std_logic

Port

IEEE

IEEE

Library

ieee

ieee

Library

ipbus

ipbus

Package

ipbus_decode_glib_v3_basex

ipbus_decode_glib_v3_basex

Package

ipbus_trans_decl

ipbus_trans_decl

Package

leds

leds out std_logic_vector ( 2 downto 0 )

Port

leds_gpoi

leds_gpoi out std_logic_vector ( 7 downto 0 )

Port

mac_arbiter_decl

mac_arbiter_decl

Package

mp7_data_types

mp7_data_types

Package

mp7_readout_decl

mp7_readout_decl

Package

mp7_ttc_decl

mp7_ttc_decl

Package

numeric_std

numeric_std

Package

phy_rst

phy_rst out std_logic

Port

phy_rstb

phy_rstb out std_logic

Port

q_n

q_n out std_logic_vector ( N_OUT- 1 downto 0 )

Port

q_p

q_p out std_logic_vector ( N_OUT- 1 downto 0 )

Port

refclkn

refclkn in std_logic_vector ( N_REFCLK - 1 downto 0 )

Port

refclkp

refclkp in std_logic_vector ( N_REFCLK - 1 downto 0 )

Port

scl

scl inout std_logic

Port

sda

sda inout std_logic

Port

sfp_los

sfp_los in std_logic

Port

sgmii_clkn

sgmii_clkn in std_logic

Port

sgmii_clkp

sgmii_clkp in std_logic

Port

sgmii_rxn

sgmii_rxn in std_logic

Port

sgmii_rxp

sgmii_rxp in std_logic

Port

sgmii_txn

sgmii_txn out std_logic

Port

sgmii_txp

sgmii_txp out std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

std_logic_1164

std_logic_1164

Package

sys_clk_pin

sys_clk_pin in STD_LOGIC

Port

sysclk

sysclk in STD_LOGIC

Port

sysclk_n

sysclk_n in STD_LOGIC

Port

sysclk_p

sysclk_p in STD_LOGIC

Port

top_decl

top_decl

Package

ttc_in_n

ttc_in_n in std_logic

Port

ttc_in_p

ttc_in_p in std_logic

Port

v6_cpld

v6_cpld inout std_logic_vector ( 0 to 5 )

Port

xpoint_ctrl

xpoint_ctrl out std_logic_vector ( 9 downto 0 )

Port

---

The documentation for this class was generated from the following files:

• ipbus_lib/boards/glib/ipbus_test/glib_v3/hdl/top.vhd
• ipbus_lib/boards/glib/ipbus_test/glib_v3/hdl/top_basex.vhd
• ipbus_lib/boards/glib/ipbus_test/glib_v3/hdl/top_dual.vhd
• ipbus_lib/boards/glib/ipbus_test/glib_v3_basex/firmware/hdl/glib_v3_basex.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_atlys/top_atlys.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_kc705_basex/top_kc705_basex.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_kc705_extphy/top_kc705_extphy.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_ml605_sgmii/top_ml605_sgmii.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_sp605_basex/top_sp605_basex.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_sp605_extphy/top_sp605_extphy.vhd
• ipbus_lib/boards/ipbus_demo/orig/hdl/demo_v5fxt/top_v5fxt.vhd
• ipbus_lib/boards/ipbus_sim/hdl/top_sim.vhd
• ipbus_lib/boards/kc705/base_fw/kc705/firmware/hdl/kc705_top.vhd
• ipbus_lib/boards/xilinx_eval/base_fw/kc705_gmii/firmware/hdl/top_kc705_gmii.vhd
• ipbus_lib/boards/xilinx_eval/base_fw/sp601/firmware/hdl/top_sp601.vhd