My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
ieee | |
work |
Use Clauses | |
std_logic_1164 | |
numeric_std |
Ports | |
clk | in std_logic |
rst | in std_logic |
we | in std_logic |
addr | in std_logic_vector ( 1 downto 0 ) |
din | in std_logic_vector ( 31 downto 0 ) |
dout | out std_logic_vector ( 31 downto 0 ) |
vec_in | in std_logic_vector ( 127 downto 0 ) |
vec_out | out std_logic_vector ( 127 downto 0 ) |
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Library |
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Package |
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