My Project  v0.0.16
Ports | Libraries | Use Clauses
transactor_cfg Entity Reference
Inheritance diagram for transactor_cfg:
Inheritance graph
[legend]

Entities

rtl  architecture
 

Libraries

ieee 
work 

Use Clauses

std_logic_1164 
numeric_std 

Ports

clk   in std_logic
rst   in std_logic
we   in std_logic
addr   in std_logic_vector ( 1 downto 0 )
din   in std_logic_vector ( 31 downto 0 )
dout   out std_logic_vector ( 31 downto 0 )
vec_in   in std_logic_vector ( 127 downto 0 )
vec_out   out std_logic_vector ( 127 downto 0 )

Member Data Documentation

◆ addr

addr in std_logic_vector ( 1 downto 0 )
Port

◆ clk

clk in std_logic
Port

◆ din

din in std_logic_vector ( 31 downto 0 )
Port

◆ dout

dout out std_logic_vector ( 31 downto 0 )
Port

◆ ieee

ieee
Library

◆ numeric_std

numeric_std
Package

◆ rst

rst in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ vec_in

vec_in in std_logic_vector ( 127 downto 0 )
Port

◆ vec_out

vec_out out std_logic_vector ( 127 downto 0 )
Port

◆ we

we in std_logic
Port

◆ work

work
Library

The documentation for this class was generated from the following file: