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My Project
v0.0.16
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Entities | |
| core | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| all | |
Ports | |
| cdrclk_in_locked | in std_logic |
| cdrclk_in | in std_logic |
| cdrdata_in | in std_logic |
| single_bit_error | out std_logic |
| double_bit_error | out std_logic |
| communication_error | out std_logic |
| l1a | out std_logic |
| brc_strobe | out std_logic |
| add_strobe | out std_logic |
| brc_t2 | out std_logic_vector ( 1 downto 0 ) |
| brc_d4 | out std_logic_vector ( 3 downto 0 ) |
| brc_e | out std_logic |
| brc_b | out std_logic |
| add_a14 | out std_logic_vector ( 13 downto 0 ) |
| add_e | out std_logic |
| add_s8 | out std_logic_vector ( 7 downto 0 ) |
| add_d8 | out std_logic_vector ( 7 downto 0 ) |
| ready | out std_logic |
| div_nrst | out std_logic |
| ttc_clk_gated | out std_logic |
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1.8.13