My Project  v0.0.16
Ports | Libraries | Use Clauses
ttc_decoder_core Entity Reference
Inheritance diagram for ttc_decoder_core:
Inheritance graph
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Collaboration diagram for ttc_decoder_core:
Collaboration graph
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Entities

core  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
all  

Ports

cdrclk_in_locked   in std_logic
cdrclk_in   in std_logic
cdrdata_in   in std_logic
single_bit_error   out std_logic
double_bit_error   out std_logic
communication_error   out std_logic
l1a   out std_logic
brc_strobe   out std_logic
add_strobe   out std_logic
brc_t2   out std_logic_vector ( 1 downto 0 )
brc_d4   out std_logic_vector ( 3 downto 0 )
brc_e   out std_logic
brc_b   out std_logic
add_a14   out std_logic_vector ( 13 downto 0 )
add_e   out std_logic
add_s8   out std_logic_vector ( 7 downto 0 )
add_d8   out std_logic_vector ( 7 downto 0 )
ready   out std_logic
div_nrst   out std_logic
ttc_clk_gated   out std_logic

Member Data Documentation

◆  all

all
Package

◆ add_a14

add_a14 out std_logic_vector ( 13 downto 0 )
Port

◆ add_d8

add_d8 out std_logic_vector ( 7 downto 0 )
Port

◆ add_e

add_e out std_logic
Port

◆ add_s8

add_s8 out std_logic_vector ( 7 downto 0 )
Port

◆ add_strobe

add_strobe out std_logic
Port

◆ brc_b

brc_b out std_logic
Port

◆ brc_d4

brc_d4 out std_logic_vector ( 3 downto 0 )
Port

◆ brc_e

brc_e out std_logic
Port

◆ brc_strobe

brc_strobe out std_logic
Port

◆ brc_t2

brc_t2 out std_logic_vector ( 1 downto 0 )
Port

◆ cdrclk_in

cdrclk_in in std_logic
Port

◆ cdrclk_in_locked

cdrclk_in_locked in std_logic
Port

◆ cdrdata_in

cdrdata_in in std_logic
Port

◆ communication_error

communication_error out std_logic
Port

◆ div_nrst

div_nrst out std_logic
Port

◆ double_bit_error

double_bit_error out std_logic
Port

◆ ieee

ieee
Library

◆ l1a

l1a out std_logic
Port

◆ ready

ready out std_logic
Port

◆ single_bit_error

single_bit_error out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ std_logic_arith

std_logic_arith
Package

◆ std_logic_unsigned

◆ ttc_clk_gated

ttc_clk_gated out std_logic
Port

The documentation for this class was generated from the following file: