My Project  v0.0.16
Ports | Libraries | Use Clauses
udp_build_ping Entity Reference
Inheritance diagram for udp_build_ping:
Inheritance graph
[legend]

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Ports

mac_clk   in std_logic
rx_reset   in std_logic
my_rx_data   in std_logic_vector ( 7 downto 0 )
my_rx_valid   in std_logic
my_rx_last   in std_logic
my_rx_error   in std_logic
pkt_drop_ping   in std_logic
outbyte   in std_logic_vector ( 7 downto 0 )
ping_data   out std_logic_vector ( 7 downto 0 )
ping_addr   out std_logic_vector ( 12 downto 0 )
ping_we   out std_logic
ping_end_addr   out std_logic_vector ( 12 downto 0 )
ping_send   out std_logic
do_sum_ping   out std_logic
clr_sum_ping   out std_logic
int_data_ping   out std_logic_vector ( 7 downto 0 )
int_valid_ping   out std_logic

Member Data Documentation

◆ clr_sum_ping

clr_sum_ping out std_logic
Port

◆ do_sum_ping

do_sum_ping out std_logic
Port

◆ ieee

ieee
Library

◆ int_data_ping

int_data_ping out std_logic_vector ( 7 downto 0 )
Port

◆ int_valid_ping

int_valid_ping out std_logic
Port

◆ mac_clk

mac_clk in std_logic
Port

◆ my_rx_data

my_rx_data in std_logic_vector ( 7 downto 0 )
Port

◆ my_rx_error

my_rx_error in std_logic
Port

◆ my_rx_last

my_rx_last in std_logic
Port

◆ my_rx_valid

my_rx_valid in std_logic
Port

◆ numeric_std

numeric_std
Package

◆ outbyte

outbyte in std_logic_vector ( 7 downto 0 )
Port

◆ ping_addr

ping_addr out std_logic_vector ( 12 downto 0 )
Port

◆ ping_data

ping_data out std_logic_vector ( 7 downto 0 )
Port

◆ ping_end_addr

ping_end_addr out std_logic_vector ( 12 downto 0 )
Port

◆ ping_send

ping_send out std_logic
Port

◆ ping_we

ping_we out std_logic
Port

◆ pkt_drop_ping

pkt_drop_ping in std_logic
Port

◆ rx_reset

rx_reset in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

The documentation for this class was generated from the following file: