My Project  v0.0.16
Ports | Libraries | Use Clauses
udp_byte_sum Entity Reference
Inheritance diagram for udp_byte_sum:
Inheritance graph
[legend]

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Ports

mac_clk   in std_logic
do_sum   in std_logic
clr_sum   in std_logic
my_rx_data   in std_logic_vector ( 7 downto 0 )
my_rx_valid   in std_logic
int_data   in std_logic_vector ( 7 downto 0 )
int_valid   in std_logic
cksum   in std_logic
run_byte_sum   in std_logic
outbyte   out std_logic_vector ( 7 downto 0 )

Member Data Documentation

◆ cksum

cksum in std_logic
Port

◆ clr_sum

clr_sum in std_logic
Port

◆ do_sum

do_sum in std_logic
Port

◆ ieee

ieee
Library

◆ int_data

int_data in std_logic_vector ( 7 downto 0 )
Port

◆ int_valid

int_valid in std_logic
Port

◆ mac_clk

mac_clk in std_logic
Port

◆ my_rx_data

my_rx_data in std_logic_vector ( 7 downto 0 )
Port

◆ my_rx_valid

my_rx_valid in std_logic
Port

◆ numeric_std

numeric_std
Package

◆ outbyte

outbyte out std_logic_vector ( 7 downto 0 )
Port

◆ run_byte_sum

run_byte_sum in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

The documentation for this class was generated from the following file: