|
My Project
v0.0.16
|

Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
Ports | |
| mac_clk | in std_logic |
| do_sum | in std_logic |
| clr_sum | in std_logic |
| my_rx_data | in std_logic_vector ( 7 downto 0 ) |
| my_rx_valid | in std_logic |
| int_data | in std_logic_vector ( 7 downto 0 ) |
| int_valid | in std_logic |
| cksum | in std_logic |
| run_byte_sum | in std_logic |
| outbyte | out std_logic_vector ( 7 downto 0 ) |
|
Port |
|
Port |
|
Port |
|
Library |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Package |
|
Port |
|
Port |
|
Package |
1.8.13