udp_clock_crossing_if Entity Reference

Inheritance diagram for udp_clock_crossing_if:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
BUFWIDTH	natural := 0

Ports
mac_clk	in std_logic
rst_macclk_reg	in std_logic
busy_125	in std_logic
rx_read_buffer_125	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rx_req_send_125	in std_logic
tx_write_buffer_125	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
enable_125	out std_logic
rarp_125	out std_logic
rst_ipb_125	out std_logic
rx_ram_sent	out std_logic
tx_ram_written	out std_logic
we_125	out std_logic
ipb_clk	in std_logic
rst_ipb	in std_logic
enable	in std_logic
pkt_done_read	in std_logic
pkt_done_write	in std_logic
RARP	in std_logic
we	in std_logic
busy	out std_logic
pkt_rdy	out std_logic
rx_read_buffer	out std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_write_buffer	out std_logic_vector ( BUFWIDTH - 1 downto 0 )

Member Data Documentation

BUFWIDTH

BUFWIDTH natural := 0

Generic

busy

busy out std_logic

Port

busy_125

busy_125 in std_logic

Port

enable

enable in std_logic

Port

enable_125

enable_125 out std_logic

Port

ieee

ieee

Library

ipb_clk

ipb_clk in std_logic

Port

mac_clk

mac_clk in std_logic

Port

numeric_std

numeric_std

Package

pkt_done_read

pkt_done_read in std_logic

Port

pkt_done_write

pkt_done_write in std_logic

Port

pkt_rdy

pkt_rdy out std_logic

Port

RARP

RARP in std_logic

Port

rarp_125

rarp_125 out std_logic

Port

rst_ipb

rst_ipb in std_logic

Port

rst_ipb_125

rst_ipb_125 out std_logic

Port

rst_macclk_reg

rst_macclk_reg in std_logic

Port

rx_ram_sent

rx_ram_sent out std_logic

Port

rx_read_buffer

rx_read_buffer out std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

rx_read_buffer_125

rx_read_buffer_125 in std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

rx_req_send_125

rx_req_send_125 in std_logic

Port

std_logic_1164

std_logic_1164

Package

tx_ram_written

tx_ram_written out std_logic

Port

tx_write_buffer

tx_write_buffer out std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

tx_write_buffer_125

tx_write_buffer_125 in std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

we

we in std_logic

Port

we_125

we_125 out std_logic

Port

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd