udp_tx_mux Entity Reference

Inheritance diagram for udp_tx_mux:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
INTERNAL_ONLY	std_logic := ' 0 '

Ports
mac_clk	in std_logic
rst_macclk_reg	in std_logic
rxram_end_addr	in std_logic_vector ( 12 downto 0 )
rxram_send	in std_logic
rxram_busy	out std_logic
addrb	out std_logic_vector ( 12 downto 0 )
dob	in std_logic_vector ( 7 downto 0 )
udpram_send	in std_logic
udpram_busy	out std_logic
udpaddrb	out std_logic_vector ( 12 downto 0 )
udpdob	in std_logic_vector ( 7 downto 0 )
do_sum	out std_logic
clr_sum	out std_logic
int_data	out std_logic_vector ( 7 downto 0 )
int_valid	out std_logic
cksum	out std_logic
outbyte	in std_logic_vector ( 7 downto 0 )
mac_tx_data	out std_logic_vector ( 7 downto 0 )
mac_tx_valid	out std_logic
mac_tx_last	out std_logic
mac_tx_error	out std_logic
mac_tx_ready	in std_logic
ipbus_out_hdr	out std_logic_vector ( 31 downto 0 )
ipbus_out_valid	out std_logic

Member Data Documentation

addrb

addrb out std_logic_vector ( 12 downto 0 )

Port

cksum

cksum out std_logic

Port

clr_sum

clr_sum out std_logic

Port

do_sum

do_sum out std_logic

Port

dob

dob in std_logic_vector ( 7 downto 0 )

Port

ieee

ieee

Library

int_data

int_data out std_logic_vector ( 7 downto 0 )

Port

int_valid

int_valid out std_logic

Port

INTERNAL_ONLY

INTERNAL_ONLY std_logic := ' 0 '

Generic

ipbus_out_hdr

ipbus_out_hdr out std_logic_vector ( 31 downto 0 )

Port

ipbus_out_valid

ipbus_out_valid out std_logic

Port

mac_clk

mac_clk in std_logic

Port

mac_tx_data

mac_tx_data out std_logic_vector ( 7 downto 0 )

Port

mac_tx_error

mac_tx_error out std_logic

Port

mac_tx_last

mac_tx_last out std_logic

Port

mac_tx_ready

mac_tx_ready in std_logic

Port

mac_tx_valid

mac_tx_valid out std_logic

Port

numeric_std

numeric_std

Package

outbyte

outbyte in std_logic_vector ( 7 downto 0 )

Port

rst_macclk_reg

rst_macclk_reg in std_logic

Port

rxram_busy

rxram_busy out std_logic

Port

rxram_end_addr

rxram_end_addr in std_logic_vector ( 12 downto 0 )

Port

rxram_send

rxram_send in std_logic

Port

std_logic_1164

std_logic_1164

Package

udpaddrb

udpaddrb out std_logic_vector ( 12 downto 0 )

Port

udpdob

udpdob in std_logic_vector ( 7 downto 0 )

Port

udpram_busy

udpram_busy out std_logic

Port

udpram_send

udpram_send in std_logic

Port

---

The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_tx_mux.vhd