My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
udp_txtransactor_if Entity Reference
Inheritance diagram for udp_txtransactor_if:
Inheritance graph
[legend]

Entities

simple  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

BUFWIDTH  natural := 0

Ports

mac_clk   in std_logic
rst_macclk_reg   in std_logic
pkt_resend   in std_logic
resend_pkt_id   in std_logic_vector ( 15 downto 0 )
ipbus_out_hdr   in std_logic_vector ( 31 downto 0 )
ipbus_out_valid   in std_logic
tx_read_buffer   in std_logic_vector ( BUFWIDTH - 1 downto 0 )
udpram_busy   in std_logic
clean_buf   in std_logic_vector ( 2 ** BUFWIDTH - 1 downto 0 )
req_not_found   out std_logic
req_resend   out std_logic
resend_buf   out std_logic_vector ( BUFWIDTH - 1 downto 0 )
udpram_sent   out std_logic

Member Data Documentation

◆ BUFWIDTH

BUFWIDTH natural := 0
Generic

◆ clean_buf

clean_buf in std_logic_vector ( 2 ** BUFWIDTH - 1 downto 0 )
Port

◆ ieee

ieee
Library

◆ ipbus_out_hdr

ipbus_out_hdr in std_logic_vector ( 31 downto 0 )
Port

◆ ipbus_out_valid

ipbus_out_valid in std_logic
Port

◆ mac_clk

mac_clk in std_logic
Port

◆ numeric_std

numeric_std
Package

◆ pkt_resend

pkt_resend in std_logic
Port

◆ req_not_found

req_not_found out std_logic
Port

◆ req_resend

req_resend out std_logic
Port

◆ resend_buf

resend_buf out std_logic_vector ( BUFWIDTH - 1 downto 0 )
Port

◆ resend_pkt_id

resend_pkt_id in std_logic_vector ( 15 downto 0 )
Port

◆ rst_macclk_reg

rst_macclk_reg in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ tx_read_buffer

tx_read_buffer in std_logic_vector ( BUFWIDTH - 1 downto 0 )
Port

◆ udpram_busy

udpram_busy in std_logic
Port

◆ udpram_sent

udpram_sent out std_logic
Port

The documentation for this class was generated from the following file: