v5_emac_v1_8 Entity Reference

Inheritance diagram for v5_emac_v1_8:

Entities
WRAPPER	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
EMAC0CLIENTRXCLIENTCLKOUT	out std_logic
CLIENTEMAC0RXCLIENTCLKIN	in std_logic
EMAC0CLIENTRXD	out std_logic_vector ( 7 downto 0 )
EMAC0CLIENTRXDVLD	out std_logic
EMAC0CLIENTRXDVLDMSW	out std_logic
EMAC0CLIENTRXGOODFRAME	out std_logic
EMAC0CLIENTRXBADFRAME	out std_logic
EMAC0CLIENTRXFRAMEDROP	out std_logic
EMAC0CLIENTRXSTATS	out std_logic_vector ( 6 downto 0 )
EMAC0CLIENTRXSTATSVLD	out std_logic
EMAC0CLIENTRXSTATSBYTEVLD	out std_logic
EMAC0CLIENTTXCLIENTCLKOUT	out std_logic
CLIENTEMAC0TXCLIENTCLKIN	in std_logic
CLIENTEMAC0TXD	in std_logic_vector ( 7 downto 0 )
CLIENTEMAC0TXDVLD	in std_logic
CLIENTEMAC0TXDVLDMSW	in std_logic
EMAC0CLIENTTXACK	out std_logic
CLIENTEMAC0TXFIRSTBYTE	in std_logic
CLIENTEMAC0TXUNDERRUN	in std_logic
EMAC0CLIENTTXCOLLISION	out std_logic
EMAC0CLIENTTXRETRANSMIT	out std_logic
CLIENTEMAC0TXIFGDELAY	in std_logic_vector ( 7 downto 0 )
EMAC0CLIENTTXSTATS	out std_logic
EMAC0CLIENTTXSTATSVLD	out std_logic
EMAC0CLIENTTXSTATSBYTEVLD	out std_logic
CLIENTEMAC0PAUSEREQ	in std_logic
CLIENTEMAC0PAUSEVAL	in std_logic_vector ( 15 downto 0 )
GTX_CLK_0	in std_logic
PHYEMAC0TXGMIIMIICLKIN	in std_logic
EMAC0PHYTXGMIIMIICLKOUT	out std_logic
GMII_TXD_0	out std_logic_vector ( 7 downto 0 )
GMII_TX_EN_0	out std_logic
GMII_TX_ER_0	out std_logic
GMII_RXD_0	in std_logic_vector ( 7 downto 0 )
GMII_RX_DV_0	in std_logic
GMII_RX_ER_0	in std_logic
GMII_RX_CLK_0	in std_logic
DCM_LOCKED_0	in std_logic
RESET	in std_logic

Member Data Documentation

CLIENTEMAC0PAUSEREQ

CLIENTEMAC0PAUSEREQ in std_logic

Port

CLIENTEMAC0PAUSEVAL

CLIENTEMAC0PAUSEVAL in std_logic_vector ( 15 downto 0 )

Port

CLIENTEMAC0RXCLIENTCLKIN

CLIENTEMAC0RXCLIENTCLKIN in std_logic

Port

CLIENTEMAC0TXCLIENTCLKIN

CLIENTEMAC0TXCLIENTCLKIN in std_logic

Port

CLIENTEMAC0TXD

CLIENTEMAC0TXD in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXDVLD

CLIENTEMAC0TXDVLD in std_logic

Port

CLIENTEMAC0TXDVLDMSW

CLIENTEMAC0TXDVLDMSW in std_logic

Port

CLIENTEMAC0TXFIRSTBYTE

CLIENTEMAC0TXFIRSTBYTE in std_logic

Port

CLIENTEMAC0TXIFGDELAY

CLIENTEMAC0TXIFGDELAY in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXUNDERRUN

CLIENTEMAC0TXUNDERRUN in std_logic

Port

DCM_LOCKED_0

DCM_LOCKED_0 in std_logic

Port

EMAC0CLIENTRXBADFRAME

EMAC0CLIENTRXBADFRAME out std_logic

Port

EMAC0CLIENTRXCLIENTCLKOUT

EMAC0CLIENTRXCLIENTCLKOUT out std_logic

Port

EMAC0CLIENTRXD

EMAC0CLIENTRXD out std_logic_vector ( 7 downto 0 )

Port

EMAC0CLIENTRXDVLD

EMAC0CLIENTRXDVLD out std_logic

Port

EMAC0CLIENTRXDVLDMSW

EMAC0CLIENTRXDVLDMSW out std_logic

Port

EMAC0CLIENTRXFRAMEDROP

EMAC0CLIENTRXFRAMEDROP out std_logic

Port

EMAC0CLIENTRXGOODFRAME

EMAC0CLIENTRXGOODFRAME out std_logic

Port

EMAC0CLIENTRXSTATS

EMAC0CLIENTRXSTATS out std_logic_vector ( 6 downto 0 )

Port

EMAC0CLIENTRXSTATSBYTEVLD

EMAC0CLIENTRXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTRXSTATSVLD

EMAC0CLIENTRXSTATSVLD out std_logic

Port

EMAC0CLIENTTXACK

EMAC0CLIENTTXACK out std_logic

Port

EMAC0CLIENTTXCLIENTCLKOUT

EMAC0CLIENTTXCLIENTCLKOUT out std_logic

Port

EMAC0CLIENTTXCOLLISION

EMAC0CLIENTTXCOLLISION out std_logic

Port

EMAC0CLIENTTXRETRANSMIT

EMAC0CLIENTTXRETRANSMIT out std_logic

Port

EMAC0CLIENTTXSTATS

EMAC0CLIENTTXSTATS out std_logic

Port

EMAC0CLIENTTXSTATSBYTEVLD

EMAC0CLIENTTXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTTXSTATSVLD

EMAC0CLIENTTXSTATSVLD out std_logic

Port

EMAC0PHYTXGMIIMIICLKOUT

EMAC0PHYTXGMIIMIICLKOUT out std_logic

Port

GMII_RX_CLK_0

GMII_RX_CLK_0 in std_logic

Port

GMII_RX_DV_0

GMII_RX_DV_0 in std_logic

Port

GMII_RX_ER_0

GMII_RX_ER_0 in std_logic

Port

GMII_RXD_0

GMII_RXD_0 in std_logic_vector ( 7 downto 0 )

Port

GMII_TX_EN_0

GMII_TX_EN_0 out std_logic

Port

GMII_TX_ER_0

GMII_TX_ER_0 out std_logic

Port

GMII_TXD_0

GMII_TXD_0 out std_logic_vector ( 7 downto 0 )

Port

GTX_CLK_0

GTX_CLK_0 in std_logic

Port

ieee

ieee

Library

PHYEMAC0TXGMIIMIICLKIN

PHYEMAC0TXGMIIMIICLKIN in std_logic

Port

RESET

RESET in std_logic

Port

std_logic_1164

std_logic_1164

Package

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8/v5_emac_v1_8.vhd