v6_emac_v2_3_basex_block Entity Reference

Inheritance diagram for v6_emac_v2_3_basex_block:

Collaboration diagram for v6_emac_v2_3_basex_block:

Entities
TOP_LEVEL	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
gtx_clk	in std_logic
clk125_out	out std_logic
rx_statistics_vector	out std_logic_vector ( 27 downto 0 )
rx_statistics_valid	out std_logic
rx_reset	out std_logic
rx_axis_mac_tdata	out std_logic_vector ( 7 downto 0 )
rx_axis_mac_tvalid	out std_logic
rx_axis_mac_tlast	out std_logic
rx_axis_mac_tuser	out std_logic
tx_ifg_delay	in std_logic_vector ( 7 downto 0 )
tx_statistics_vector	out std_logic_vector ( 31 downto 0 )
tx_statistics_valid	out std_logic
tx_reset	out std_logic
tx_axis_mac_tdata	in std_logic_vector ( 7 downto 0 )
tx_axis_mac_tvalid	in std_logic
tx_axis_mac_tlast	in std_logic
tx_axis_mac_tuser	in std_logic
tx_axis_mac_tready	out std_logic
tx_collision	out std_logic
tx_retransmit	out std_logic
pause_req	in std_logic
pause_val	in std_logic_vector ( 15 downto 0 )
txp	out std_logic
txn	out std_logic
rxp	in std_logic
rxn	in std_logic
phyad	in std_logic_vector ( 4 downto 0 )
resetdone	out std_logic
syncacqstatus	out std_logic
clk_ds	in std_logic
glbl_rstn	in std_logic
rx_axi_rstn	in std_logic
tx_axi_rstn	in std_logic

Member Data Documentation

clk125_out

clk125_out out std_logic

Port

clk_ds

clk_ds in std_logic

Port

glbl_rstn

glbl_rstn in std_logic

Port

gtx_clk

gtx_clk in std_logic

Port

ieee

ieee

Library

pause_req

pause_req in std_logic

Port

pause_val

pause_val in std_logic_vector ( 15 downto 0 )

Port

phyad

phyad in std_logic_vector ( 4 downto 0 )

Port

resetdone

resetdone out std_logic

Port

rx_axi_rstn

rx_axi_rstn in std_logic

Port

rx_axis_mac_tdata

rx_axis_mac_tdata out std_logic_vector ( 7 downto 0 )

Port

rx_axis_mac_tlast

rx_axis_mac_tlast out std_logic

Port

rx_axis_mac_tuser

rx_axis_mac_tuser out std_logic

Port

rx_axis_mac_tvalid

rx_axis_mac_tvalid out std_logic

Port

rx_reset

rx_reset out std_logic

Port

rx_statistics_valid

rx_statistics_valid out std_logic

Port

rx_statistics_vector

rx_statistics_vector out std_logic_vector ( 27 downto 0 )

Port

rxn

rxn in std_logic

Port

rxp

rxp in std_logic

Port

std_logic_1164

std_logic_1164

Package

syncacqstatus

syncacqstatus out std_logic

Port

tx_axi_rstn

tx_axi_rstn in std_logic

Port

tx_axis_mac_tdata

tx_axis_mac_tdata in std_logic_vector ( 7 downto 0 )

Port

tx_axis_mac_tlast

tx_axis_mac_tlast in std_logic

Port

tx_axis_mac_tready

tx_axis_mac_tready out std_logic

Port

tx_axis_mac_tuser

tx_axis_mac_tuser in std_logic

Port

tx_axis_mac_tvalid

tx_axis_mac_tvalid in std_logic

Port

tx_collision

tx_collision out std_logic

Port

tx_ifg_delay

tx_ifg_delay in std_logic_vector ( 7 downto 0 )

Port

tx_reset

tx_reset out std_logic

Port

tx_retransmit

tx_retransmit out std_logic

Port

tx_statistics_valid

tx_statistics_valid out std_logic

Port

tx_statistics_vector

tx_statistics_vector out std_logic_vector ( 31 downto 0 )

Port

txn

txn out std_logic

Port

txp

txp out std_logic

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v6_emac_v2_3_basex/v6_emac_v2_3_basex_block.vhd