Constraints
eth/clk125_out	TNM_NET = clk125
TS_clk125	PERIOD clk125 8ns
clocks/rst	TIG
clocks/nuke_i	TIG
gt_clkp	LOC = M6 \| DIFF_TERM = TRUE \| TNM_NET = gtpclk
gt_clkn	LOC = M5 \| DIFF_TERM = TRUE
TS_gtpclk	PERIOD gtpclk 8ns
eth/*/gtxe1_i	LOC = GTXE1_X0Y9
leds<0>	LOC = AF31 \| IOSTANDARD = LVCMOS25
leds<1>	LOC = AB25 \| IOSTANDARD = LVCMOS25
leds<2>	LOC = AC25 \| IOSTANDARD = LVCMOS25
LOC = AE32	"v6_cpld[0]" IO_L14N_VREF_13
LOC = AB27	"v6_cpld[1]" IO_L15P_13
LOC = AC27	"v6_cpld[2]" IO_L15N_13
LOC = AG33	"v6_cpld[3]" IO_L16P_13
LOC = AG32	"v6_cpld[4]" IO_L16N_13
LOC = AA26	"v6_cpld[5]" IO_L17P_13
sda	LOC = AP21
scl	LOC = AP20

Variable Documentation

◆ "v6_cpld[0]"

"v6_cpld[0]" LOC = AE32 IO_L14N_VREF_13

Constraints

◆ "v6_cpld[1]"

"v6_cpld[1]" LOC = AB27 IO_L15P_13

Constraints

◆ "v6_cpld[2]"

"v6_cpld[2]" LOC = AC27 IO_L15N_13

Constraints

◆ "v6_cpld[3]"

"v6_cpld[3]" LOC = AG33 IO_L16P_13

Constraints

◆ "v6_cpld[4]"

"v6_cpld[4]" LOC = AG32 IO_L16N_13

Constraints

◆ "v6_cpld[5]"

"v6_cpld[5]" LOC = AA26 IO_L17P_13

Constraints

◆ clocks/nuke_i

clocks/nuke_i TIG

Constraints

◆ clocks/rst

clocks/rst TIG

Constraints

◆ eth/*/gtxe1_i

eth/*/gtxe1_i LOC = GTXE1_X0Y9

Constraints

◆ eth/clk125_out

eth/clk125_out TNM_NET = clk125

Constraints

◆ gt_clkn

gt_clkn LOC = M5 | DIFF_TERM = TRUE

Constraints

◆ gt_clkp

gt_clkp LOC = M6 | DIFF_TERM = TRUE | TNM_NET = gtpclk

Constraints

◆ leds<0>

leds<0> LOC = AF31 | IOSTANDARD = LVCMOS25

Constraints

◆ leds<1>

leds<1> LOC = AB25 | IOSTANDARD = LVCMOS25

Constraints

◆ leds<2>

leds<2> LOC = AC25 | IOSTANDARD = LVCMOS25

Constraints

◆ scl

scl LOC = AP20

Constraints

◆ sda

sda LOC = AP21

Constraints

◆ TS_clk125

TS_clk125 PERIOD clk125 8ns

Constraints

◆ TS_gtpclk

TS_gtpclk PERIOD gtpclk 8ns

Constraints