RTL Architecture Reference

Processes
PROCESS_97	( clock )
PROCESS_98	( clock )

Components
onehot_dec	<Entity onehot_dec>

Signals
nxt_chan	std_logic
pointer	std_logic_vector ( 31 downto 0 )
tvalid	std_logic
chan_count	std_logic_vector ( 4 downto 0 ) := " 00000 "
m_tdata_pipe	STD_LOGIC_VECTOR ( ( bp_width- 1 ) downto 0 )
m_tvalid_pipe	STD_LOGIC
m_tlast_pipe	STD_LOGIC
m_header_mark_pipe	STD_LOGIC
m_trailer_mark_pipe	STD_LOGIC
m_hdr_crc_tag_pipe	STD_LOGIC
m_tdata_pipe_reg	STD_LOGIC_VECTOR ( ( bp_width- 1 ) downto 0 )
m_tvalid_pipe_reg	STD_LOGIC
m_tlast_pipe_reg	STD_LOGIC
m_header_mark_pipe_reg	STD_LOGIC
m_trailer_mark_pipe_reg	STD_LOGIC
m_hdr_crc_tag_pipe_reg	STD_LOGIC

Instantiations
chan_dec	onehot_dec <Entity onehot_dec>

Detailed Description

Definition at line 330 of file channel_mux.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/channel_mux.vhd