tob_processor Entity Reference

Inheritance diagram for tob_processor:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
ipbus
ipbus_decode_L1CaloHubRodTobProc

Generics
sim	integer := 0
jfex	integer := 0
CRC20_G_Poly	std_logic_vector ( 19 downto 0 ) := x " 8349f "
timeout_1_default	std_logic_vector ( 15 downto 0 ) := x " 0600 "
timeout_n_default	std_logic_vector ( 15 downto 0 ) := x " 0030 "
wdog_thresh_default	std_logic_vector ( 15 downto 0 ) := x " 2000 "
C_S_AXI_DATA_WIDTH	integer := 32
C_S_AXI_ADDR_WIDTH	integer := 9
bp_width	integer := 64
header_width	integer := 64
event_width	integer := 64

Ports
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
geo_location	in	STD_LOGIC_VECTOR ( 7 downto 0 )
event_sel	in	STD_LOGIC_VECTOR ( 1 downto 0 )
rod_slot	in	std_logic
full_mode_ctrl	out	STD_LOGIC_VECTOR ( 31 downto 0 )
full_mode_stat	in	STD_LOGIC_VECTOR ( 31 downto 0 )
FM_L1id_stat	in	std_logic_vector ( 31 downto 0 )
stage_fifo_level	in	std_logic_vector ( 15 downto 0 )
stage_fifo_busy	out	STD_LOGIC
stage_fifo_xoff	out	STD_LOGIC
stage_fifo_full	in	STD_LOGIC
flx_backpressure	in	STD_LOGIC_vector ( 11 downto 0 )
flx_backpressure_tob	out	STD_LOGIC
pp_clock	in	STD_LOGIC
rt_clk	in	std_logic
system_reset	in	STD_LOGIC
proc_reset	in	STD_LOGIC
wdog_fifo_reset	out	STD_LOGIC
first_chan	in	STD_LOGIC_VECTOR ( 4 downto 0 )
last_chan	in	STD_LOGIC_VECTOR ( 4 downto 0 )
TTC_ignore	in	STD_LOGIC
master_header	in	STD_LOGIC_VECTOR ( 63 downto 0 )
header_fifo_valid	in	STD_LOGIC
header_read_en	out	std_logic
header_sequence	in	STD_LOGIC_VECTOR ( 11 downto 0 )
header_type	in	STD_LOGIC_VECTOR ( 3 downto 0 )
timeout_err_out	out	std_logic
m_tvalid	out	STD_LOGIC
m_tlast	out	STD_LOGIC
m_tdata	out	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
m_header_marker	out	STD_LOGIC
m_tail_marker	out	STD_LOGIC
m_tready	in	STD_LOGIC
ttc_rollover	out	std_logic
l1id_mis_stretch	out	std_logic
s_tdata_0	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_0	in	STD_LOGIC
s_tlast_0	in	STD_LOGIC
s_tready_0	out	STD_LOGIC
s_header_mark_0	in	STD_LOGIC
s_trailer_mark_0	in	STD_LOGIC
s_hdr_crc_tag_0	in	STD_LOGIC
s_poll_chan_0	out	STD_LOGIC
s_chan_enable_0	in	STD_LOGIC
s_tdata_1	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_1	in	STD_LOGIC
s_tlast_1	in	STD_LOGIC
s_tready_1	out	STD_LOGIC
s_header_mark_1	in	STD_LOGIC
s_trailer_mark_1	in	STD_LOGIC
s_hdr_crc_tag_1	in	STD_LOGIC
s_poll_chan_1	out	STD_LOGIC
s_chan_enable_1	in	STD_LOGIC
s_tdata_2	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_2	in	STD_LOGIC
s_tlast_2	in	STD_LOGIC
s_tready_2	out	STD_LOGIC
s_header_mark_2	in	STD_LOGIC
s_trailer_mark_2	in	STD_LOGIC
s_hdr_crc_tag_2	in	STD_LOGIC
s_poll_chan_2	out	STD_LOGIC
s_chan_enable_2	in	STD_LOGIC
s_tdata_3	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_3	in	STD_LOGIC
s_tlast_3	in	STD_LOGIC
s_tready_3	out	STD_LOGIC
s_header_mark_3	in	STD_LOGIC
s_trailer_mark_3	in	STD_LOGIC
s_hdr_crc_tag_3	in	STD_LOGIC
s_poll_chan_3	out	STD_LOGIC
s_chan_enable_3	in	STD_LOGIC
s_tdata_4	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_4	in	STD_LOGIC
s_tlast_4	in	STD_LOGIC
s_tready_4	out	STD_LOGIC
s_header_mark_4	in	STD_LOGIC
s_trailer_mark_4	in	STD_LOGIC
s_hdr_crc_tag_4	in	STD_LOGIC
s_poll_chan_4	out	STD_LOGIC
s_chan_enable_4	in	STD_LOGIC
s_tdata_5	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_5	in	STD_LOGIC
s_tlast_5	in	STD_LOGIC
s_tready_5	out	STD_LOGIC
s_header_mark_5	in	STD_LOGIC
s_trailer_mark_5	in	STD_LOGIC
s_hdr_crc_tag_5	in	STD_LOGIC
s_poll_chan_5	out	STD_LOGIC
s_chan_enable_5	in	STD_LOGIC
s_tdata_6	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_6	in	STD_LOGIC
s_tlast_6	in	STD_LOGIC
s_tready_6	out	STD_LOGIC
s_header_mark_6	in	STD_LOGIC
s_trailer_mark_6	in	STD_LOGIC
s_hdr_crc_tag_6	in	STD_LOGIC
s_poll_chan_6	out	STD_LOGIC
s_chan_enable_6	in	STD_LOGIC
s_tdata_7	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_7	in	STD_LOGIC
s_tlast_7	in	STD_LOGIC
s_tready_7	out	STD_LOGIC
s_header_mark_7	in	STD_LOGIC
s_trailer_mark_7	in	STD_LOGIC
s_hdr_crc_tag_7	in	STD_LOGIC
s_poll_chan_7	out	STD_LOGIC
s_chan_enable_7	in	STD_LOGIC
s_tdata_8	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_8	in	STD_LOGIC
s_tlast_8	in	STD_LOGIC
s_tready_8	out	STD_LOGIC
s_header_mark_8	in	STD_LOGIC
s_trailer_mark_8	in	STD_LOGIC
s_hdr_crc_tag_8	in	STD_LOGIC
s_poll_chan_8	out	STD_LOGIC
s_chan_enable_8	in	STD_LOGIC
s_tdata_9	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_9	in	STD_LOGIC
s_tlast_9	in	STD_LOGIC
s_tready_9	out	STD_LOGIC
s_header_mark_9	in	STD_LOGIC
s_trailer_mark_9	in	STD_LOGIC
s_hdr_crc_tag_9	in	STD_LOGIC
s_poll_chan_9	out	STD_LOGIC
s_chan_enable_9	in	STD_LOGIC
s_tdata_10	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_10	in	STD_LOGIC
s_tlast_10	in	STD_LOGIC
s_tready_10	out	STD_LOGIC
s_header_mark_10	in	STD_LOGIC
s_trailer_mark_10	in	STD_LOGIC
s_hdr_crc_tag_10	in	STD_LOGIC
s_poll_chan_10	out	STD_LOGIC
s_chan_enable_10	in	STD_LOGIC
s_tdata_11	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_11	in	STD_LOGIC
s_tlast_11	in	STD_LOGIC
s_tready_11	out	STD_LOGIC
s_header_mark_11	in	STD_LOGIC
s_trailer_mark_11	in	STD_LOGIC
s_hdr_crc_tag_11	in	STD_LOGIC
s_poll_chan_11	out	STD_LOGIC
s_chan_enable_11	in	STD_LOGIC
s_tdata_12	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_12	in	STD_LOGIC
s_tlast_12	in	STD_LOGIC
s_tready_12	out	STD_LOGIC
s_header_mark_12	in	STD_LOGIC
s_trailer_mark_12	in	STD_LOGIC
s_hdr_crc_tag_12	in	STD_LOGIC
s_poll_chan_12	out	STD_LOGIC
s_chan_enable_12	in	STD_LOGIC
s_tdata_13	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_13	in	STD_LOGIC
s_tlast_13	in	STD_LOGIC
s_tready_13	out	STD_LOGIC
s_header_mark_13	in	STD_LOGIC
s_trailer_mark_13	in	STD_LOGIC
s_hdr_crc_tag_13	in	STD_LOGIC
s_poll_chan_13	out	STD_LOGIC
s_chan_enable_13	in	STD_LOGIC
s_tdata_14	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_14	in	STD_LOGIC
s_tlast_14	in	STD_LOGIC
s_tready_14	out	STD_LOGIC
s_header_mark_14	in	STD_LOGIC
s_trailer_mark_14	in	STD_LOGIC
s_hdr_crc_tag_14	in	STD_LOGIC
s_poll_chan_14	out	STD_LOGIC
s_chan_enable_14	in	STD_LOGIC
s_tdata_15	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_15	in	STD_LOGIC
s_tlast_15	in	STD_LOGIC
s_tready_15	out	STD_LOGIC
s_header_mark_15	in	STD_LOGIC
s_trailer_mark_15	in	STD_LOGIC
s_hdr_crc_tag_15	in	STD_LOGIC
s_poll_chan_15	out	STD_LOGIC
s_chan_enable_15	in	STD_LOGIC
s_tdata_16	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_16	in	STD_LOGIC
s_tlast_16	in	STD_LOGIC
s_tready_16	out	STD_LOGIC
s_header_mark_16	in	STD_LOGIC
s_trailer_mark_16	in	STD_LOGIC
s_hdr_crc_tag_16	in	STD_LOGIC
s_poll_chan_16	out	STD_LOGIC
s_chan_enable_16	in	STD_LOGIC
s_tdata_17	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_17	in	STD_LOGIC
s_tlast_17	in	STD_LOGIC
s_tready_17	out	STD_LOGIC
s_header_mark_17	in	STD_LOGIC
s_trailer_mark_17	in	STD_LOGIC
s_hdr_crc_tag_17	in	STD_LOGIC
s_poll_chan_17	out	STD_LOGIC
s_chan_enable_17	in	STD_LOGIC
s_tdata_18	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_18	in	STD_LOGIC
s_tlast_18	in	STD_LOGIC
s_tready_18	out	STD_LOGIC
s_header_mark_18	in	STD_LOGIC
s_trailer_mark_18	in	STD_LOGIC
s_hdr_crc_tag_18	in	STD_LOGIC
s_poll_chan_18	out	STD_LOGIC
s_chan_enable_18	in	STD_LOGIC
s_tdata_19	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_19	in	STD_LOGIC
s_tlast_19	in	STD_LOGIC
s_tready_19	out	STD_LOGIC
s_header_mark_19	in	STD_LOGIC
s_trailer_mark_19	in	STD_LOGIC
s_hdr_crc_tag_19	in	STD_LOGIC
s_poll_chan_19	out	STD_LOGIC
s_chan_enable_19	in	STD_LOGIC
s_tdata_20	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_20	in	STD_LOGIC
s_tlast_20	in	STD_LOGIC
s_tready_20	out	STD_LOGIC
s_header_mark_20	in	STD_LOGIC
s_trailer_mark_20	in	STD_LOGIC
s_hdr_crc_tag_20	in	STD_LOGIC
s_poll_chan_20	out	STD_LOGIC
s_chan_enable_20	in	STD_LOGIC
s_tdata_21	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_21	in	STD_LOGIC
s_tlast_21	in	STD_LOGIC
s_tready_21	out	STD_LOGIC
s_header_mark_21	in	STD_LOGIC
s_trailer_mark_21	in	STD_LOGIC
s_hdr_crc_tag_21	in	STD_LOGIC
s_poll_chan_21	out	STD_LOGIC
s_chan_enable_21	in	STD_LOGIC
s_tdata_22	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_22	in	STD_LOGIC
s_tlast_22	in	STD_LOGIC
s_tready_22	out	STD_LOGIC
s_header_mark_22	in	STD_LOGIC
s_trailer_mark_22	in	STD_LOGIC
s_hdr_crc_tag_22	in	STD_LOGIC
s_poll_chan_22	out	STD_LOGIC
s_chan_enable_22	in	STD_LOGIC
s_tdata_23	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_tvalid_23	in	STD_LOGIC
s_tlast_23	in	STD_LOGIC
s_tready_23	out	STD_LOGIC
s_header_mark_23	in	STD_LOGIC
s_trailer_mark_23	in	STD_LOGIC
s_hdr_crc_tag_23	in	STD_LOGIC
s_poll_chan_23	out	STD_LOGIC
s_chan_enable_23	in	STD_LOGIC

Detailed Description

Definition at line 38 of file tob_processor.vhd.

Member Data Documentation

IEEE

IEEE

Library

Top level TOB processor including the event builder, Input channel_mux, and register blocks The main state machine is within the Event Builder block

Definition at line 24 of file tob_processor.vhd.

---

The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/tob_processor.vhd