error_counter.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 17.04.2019 15:02:22
-- Design Name: 
-- Module Name: error_counter - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
entity error_counter is
   generic(
     cwidth: positive := 4
    );
    Port ( 
        clock : in STD_LOGIC;
        counter_reset : in STD_LOGIC;
        system_reset  : in STD_LOGIC;
        error : in STD_LOGIC;
        error_count : out STD_LOGIC_VECTOR(cwidth-1 downto 0)
        
       
        );
end error_counter;
 
architecture RTL of error_counter is
 
signal  counter : std_logic_vector(cwidth-1 downto 0); 
signal  count_max : std_logic_vector(cwidth-1 downto 0); 
 
begin
 
count_max <= (others => '1');
 
process(clock, counter_reset, system_reset)
    begin
        if (counter_reset or system_reset) = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
            counter <= (others => '0');
        elsif rising_edge(clock) then
            if (error = '1') and (counter < count_max) then 
               counter <= (counter + 1);
            else 
              counter <= counter; 
            end if; 
        end if; 
 end process;
 
 error_count(cwidth-1 downto 0) <= counter(cwidth-1 downto 0);
 
 
end RTL;