event_trailer_CRC20.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 21.09.2018 16:08:58
-- Design Name: 
-- Module Name: event_trailer_CRC20 - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
--the data input should be the event fifo input data
--when the trailer needs to be put into the crc, the sel_packet_trailer signal is activated and calc is activated
--this puts the trailer onto the fifo input, and the crc input, but fifo s_tvalid is not asserted so it doesn't go into the fifo
--the sel_packet_trailer signal also forces the crc field of the trailer to be all zeros for the calculation 
 
entity event_trailer_CRC20 is
   generic(
     crc20_G_Poly : std_logic_vector(19 downto 0) := x"8349f";   --old poly
     Nbits :  positive  := 64;
     CRC_Width        :  positive   := 20;
     G_Poly: Std_Logic_Vector :=x"c1acf";
     G_InitVal: std_logic_vector:=x"fffff"
      );
    Port ( 
     CRC   : out    std_logic_vector(CRC_Width-1 downto 0);
     Calc  : in     std_logic;
     Clock   : in     std_logic;
     S_tdata   : in     std_logic_vector(Nbits-1 downto 0);
     crc_reset : in     std_logic;
     sel_packet_trailer : in     std_logic
 
     );
end event_trailer_CRC20;
 
architecture RTL of event_trailer_CRC20 is
 
component flx_CRC is
   generic(
     Nbits :  positive  := 64;
     CRC_Width        :  positive   := 20;
     G_Poly: Std_Logic_Vector :=x"c1acf";
     G_InitVal: std_logic_vector:=x"fffff"
     );
   port(
     CRC   : out    std_logic_vector(CRC_Width-1 downto 0);
     Calc  : in     std_logic;
     Clk   : in     std_logic;
     DIn   : in     std_logic_vector(Nbits-1 downto 0);
     Reset : in     std_logic);
end component; 
 
signal data :  std_logic_vector(63 downto 0);
signal swap_data :  std_logic_vector(63 downto 0);
 
begin
 
crc_block : flx_CRC
 generic map (
     Nbits     => 64,
     CRC_Width => 20,
 --    G_Poly    => x"c1acf",
--     G_Poly    => x"8349f",
     G_Poly    => crc20_g_poly,
     G_InitVal => x"fffff"
     )
  port map (
       CRC   => CRC,
       Calc  =>  Calc,
       Clk   => Clock,
       DIn   => swap_data,
       Reset => crc_reset
       );
 
with sel_packet_trailer select
          data <= (x"00000" & s_tdata(43 downto 32) & s_tdata(31 downto 0))  when  '1',                 
                   s_tdata   when others;
 
 
swap_data(31 downto 0) <= data(63 downto 32); 
swap_data(63 downto 32) <= data(31 downto 0);
 
--the crc input may need to be registered in orded for the crc to meet timing.  This will add one more trailer build cycle
--  process (Clock) begin
--    if rising_edge (clock) then
--       data <= S_tdata; 
--    end if;   
--   end process;
 
end RTL;