ff.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 15.02.2017 17:59:11
-- Design Name: 
-- Module Name: ff - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
 
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
package ff is
use IEEE.STD_LOGIC_1164.ALL; 
 
 component vDFF is --multibit D flip-flop
  generic (n : integer := 1);  --width
  port (clk : in std_logic; 
        D : in std_logic_vector (n-1 downto 0);
        Q : out std_logic_vector (n-1 downto 0) ); 
 end component; 
 
  component sDFF is --single bit D flip-flop
  port (clk : in std_logic; 
        D : in std_logic;
        Q : out std_logic ); 
 end component; 
 
end package;  
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
 
entity vDFF is 
   generic (n : integer := 1);  --width
  port (clk : in std_logic; 
        D : in std_logic_vector (n-1 downto 0);
        Q : out std_logic_vector (n-1 downto 0) ); 
 end vDFF; 
 
 architecture impl of vDFF is 
  begin
      process (clk) begin
        if rising_edge (clk) then 
           Q <= D;
        end if; 
      end process; 
  end impl; 
 
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
  
 entity sDFF is --single bit D flip-flop
  port (clk : in std_logic; 
        D : in std_logic;
        Q : out std_logic ); 
 end sDFF;   
 
  architecture impl of sDFF is 
  begin
      process (clk) begin
        if rising_edge (clk) then 
           Q <= D;
        end if; 
      end process; 
  end impl;