l1id_cont_check.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12.10.2022 14:06:34
-- Design Name: 
-- Module Name: l1id_cont_check - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity l1id_cont_check is
    Port ( 
    
    clock           : in STD_LOGIC;
    reset           : in STD_LOGIC;
 --   clr_errors      : in STD_LOGIC;
    L1A             : in STD_LOGIC;
    ECR             : in STD_LOGIC;
    L1id            : in STD_LOGIC_vector(23 downto 0);
    ECRid           : in STD_LOGIC_vector(7 downto 0);
    
    timeout_threshold :  in STD_LOGIC_vector(31 downto 0);
    l1id_continuity_control : in STD_LOGIC_vector (31 downto 0);
    l1id_continuity_status  : out STD_LOGIC_vector (31 downto 0);
    l1id_local_miss         : out STD_LOGIC_vector (31 downto 0);
    l1id_ttc_miss         : out STD_LOGIC_vector (31 downto 0);
    l1id_error_count : out  STD_LOGIC_vector(31 downto 0);
    repeat_counter   : out  STD_LOGIC_vector(31 downto 0)
    
   
    
    
    );
end l1id_cont_check;
 
architecture RTL of l1id_cont_check is
 
signal L1id_counter         : STD_LOGIC_vector(23 downto 0);
signal ECRid_counter        : STD_LOGIC_vector(7 downto 0);
signal timeout_counter      : STD_LOGIC_vector(31 downto 0);
signal L1id_error_counter   : STD_LOGIC_vector(31 downto 0);
signal timeout_enable       : STD_LOGIC;
signal timeout              : STD_LOGIC;
signal L1id_mismatch        : STD_LOGIC;
signal l1id_compare         : STD_LOGIC;
signal ECRid_compare        : STD_LOGIC;
signal capture              : STD_LOGIC;
signal l1id_local_miss_i      : STD_LOGIC_vector (31 downto 0);
signal l1id_ttc_miss_i        : STD_LOGIC_vector (31 downto 0);
 
 
--signal l1id_continuity_control : STD_LOGIC_vector (31 downto 0);
signal clear                   : std_logic;
signal clear_s                 : std_logic;
signal clear_s_del             : std_logic;
signal armed                   : std_logic;
signal armed_s                 : std_logic;
signal armed_s_del             : std_logic;
signal armed_pulse             : std_logic;
signal armed_stat              : std_logic;
signal triggered               : std_logic;
signal l1id_del                : std_logic;
signal ECRid_del               : std_logic;
signal word_counter            : std_logic_vector (1 downto 0);
signal current_l1ID            : std_logic_vector (31 downto 0);
signal last_l1ID               : std_logic_vector (31 downto 0);
signal repeat_counter_i         : std_logic_vector (31 downto 0);
signal clear_local_l1id        : std_logic;
signal clear_local_ECRid       : std_logic;
 
COMPONENT ila_l1id_cont
 
PORT (
    clk : IN STD_LOGIC;
 
    probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);   
    probe8 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);  
    probe9 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
    probe10 :IN STD_LOGIC_VECTOR(23 DOWNTO 0);  
    probe11 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    probe12 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    probe13 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    probe14 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
  
);
END COMPONENT  ;
 
 
begin
 
 
timeout_enable <= '1';   --needed? 
clear_local_l1id <= l1id_continuity_control(4);
clear_local_ECRid <= l1id_continuity_control(5);
 
process (clock) begin
      if rising_edge (clock) then
        if reset = '1' then 
           l1id_del <= '0'; 
           l1id_compare  <= '0';
           ECRid_compare  <= '0';
        else  
           l1id_del <= l1a; 
           l1id_compare  <= l1id_del;
           ECRid_del <= ECR; 
           ECRid_compare  <= ECRid_del;
        end if;  
     end if;
end process; 
 
-- timeout counter --if timeout = 1, then don't log any errors.    
process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') or ((L1A = '1') and (word_counter = 3)) then
                timeout_counter <= (others=> '0'); 
                 timeout <= '0';          
            elsif (timeout_enable = '1') and (timeout_counter <= timeout_threshold) then
                timeout_counter <= (timeout_counter + '1');
            elsif (timeout_counter >= timeout_threshold) then   
                timeout <= '1';
            else
                timeout_counter <= timeout_counter;
                timeout <=  timeout;
                
           end if;
      end if;
 end process;
 
 
-- ttc word counter 
process (clock) begin
      if rising_edge (clock) then
        if (reset = '1') then
                word_counter <= (others=> '0');
        elsif (L1A = '1') or (ECR = '1') then 
                word_counter <= (word_counter + 1);        
        else 
                word_counter <= word_counter;
        end if;        
      end if;          
 end process;                
                
--L1ID counter 
 process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') or (clear_local_l1id = '1') then
                L1id_counter <= (others=> '0');
                         
            elsif (L1A = '1') and (timeout = '0') and (word_counter = x"2") then  --and (L1id_counter /= X"FFFFFF") 
                L1id_counter <= (L1id_counter + '1');
            elsif (L1A = '1') and (timeout = '1')  and (word_counter = x"2") then   
                 L1id_counter <= L1id;
            elsif (l1id_compare = '1') and (word_counter = x"3") and (L1id_counter /= L1ID)  then     
                L1id_counter <= L1ID;
                
            else
                L1id_counter <= L1id_counter;
                
           end if;
      end if;
 end process;
 
 
 
--L1ID error counter 
 
 process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') or (clear = '1') then
                L1id_error_counter <= (others=> '0'); 
                triggered <= '0';
                capture   <= '0';
                l1id_local_miss_i <= (others => '0');  
                l1id_ttc_miss_i   <= (others => '0'); 
           elsif (armed_pulse = '1') then 
                triggered <= '0';                  
           elsif (l1id_compare = '1')and (word_counter = x"3") and ((ECRid_counter & L1id_counter) /= (ECRid & L1ID)) and ((ECRid & L1ID) /= x"00000000") and timeout = '0' then     
                L1id_error_counter <= L1id_error_counter + '1'; 
                if (armed_stat = '1') then 
                    triggered <= '1';
                    capture <= '1';
                    l1id_local_miss_i <= ECRid_counter & l1id_counter;
                    l1id_ttc_miss_i   <= ECRid & l1id;
                 else     
                   triggered <= triggered;
                   l1id_local_miss_i <= l1id_local_miss_i;
                   l1id_ttc_miss_i   <= l1id_ttc_miss_i; 
                   capture   <= capture;
                 end if;  
            else
                L1id_error_counter <= L1id_error_counter;
--                triggered <= triggered;
--                l1id_local_miss <= l1id_local_miss;
--                l1id_ttc_miss   <= l1id_ttc_miss; 
--                capture   <= capture;
           end if;
      end if;
 end process;
 
l1id_local_miss <= l1id_local_miss_i;
l1id_ttc_miss   <= l1id_ttc_miss_i;
 
l1id_error_count <= L1id_error_counter;
 
 
--L1id compare 
process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') then
                L1id_mismatch <= '0';           
            elsif (L1id_counter /= L1id) and (timeout = '0') then
                L1id_mismatch <= '1';  
            else
                L1id_mismatch <= L1id_mismatch;
           end if;
      end if;
 end process;
 
 
--ECRID counter 
 process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') or (clear_local_ECRid = '1')then
                ECRid_counter <= (others=> '0');
                         
            elsif (ECR = '1') and (timeout = '0') and (word_counter = x"2") then  --and (L1id_counter /= X"FFFFFF") 
                ECRid_counter <= (ECRid_counter + '1');
            elsif (ECR = '1') and (timeout = '1')  and (word_counter = x"2") then   
                 ECRid_counter <= ECRid;
            elsif (l1id_compare = '1') and (word_counter = x"3") and (ECRid_counter /= ECRID)  then     
                ECRid_counter <= ECRID;
                
            else
                ECRid_counter <= ECRid_counter;
                
           end if;
      end if;
 end process;
 
 
--Duplicate L1ID checker 
process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') then
                current_l1id <= (others=> '0');
                last_l1id    <= (others=> '0');
           elsif  (word_counter = x"3")and(l1id_compare = '1') then 
                current_l1ID <= (ECRid & L1id);      
                last_L1id    <=  current_l1ID;
           end if; 
       end if;                 
end process;
 
process (clock) begin
      if rising_edge (clock) then
           if (reset = '1') or (clear = '1')then
                repeat_counter_i <= (others=> '0');
           elsif  (word_counter = x"3") and (l1id_compare = '1')and (current_l1id = (ECRid & L1id)) and (current_l1id /= x"00000000") then 
                repeat_counter_i <= (repeat_counter_i + 1);
           end if; 
       end if;          
 end process;
 
 repeat_counter  <= repeat_counter_i;
-------control and status -------------------
 
-------sample the pulse reg in the pp_clock domain ------
--armed_s samples the pulse bit running on ipb_clk
--armed_s_del sample armed_s synchronously on pp_clock
--armed_stat is the user's status flag indicating the mech is armed, but not triggered
 
--clear pulse happens on trailing edge of ipbus pulse 
process(clock) begin
  if rising_edge (clock) then
     clear_s <= l1id_continuity_control(1);
     clear_s_del <= clear_s; 
  end if;   
end process;
 
clear <= clear_s_del and not clear_s;
 
process(clock) begin
  if rising_edge (clock) then
     armed_s <= l1id_continuity_control(0);
     armed_s_del <= armed_s; 
  end if;   
end process;
 
armed_pulse <= armed_s_del and not armed_s;
 
process(clock) begin
  if rising_edge (clock) then
     if (armed_pulse = '1') then
       armed_stat <= '1';
     elsif  (triggered = '1') or (clear = '1') or (reset = '1') then   --(ipb_rst = '1') or 
       armed_stat <= '0';         
     else 
       armed_stat <= armed_stat;     
     end if;  
  end if;
end process;
 
 
l1id_continuity_status <= x"0000000" & "00" & triggered & armed_stat;
 
ila_l1id_cont_check: ila_l1id_cont 
port map (
    clk          => clock,
    probe0       => word_counter,     --2
    probe1(0)    => l1id_compare,     --1
    probe2(0)    => L1A,              --1
    probe3(0)    => ECR,              --1
    probe4(0)    => triggered,        --1
    probe5(0)    => capture,          --1
    probe6(0)    => armed_stat,       --1
    probe7(0)    => timeout,          --1
    probe8       => L1id,             --24
    probe9       => ECRID,            --8
    probe10      => L1id_counter,     --24
    probe11      => ECRID_counter,     --8
    probe12      => repeat_counter_i,  --32
    probe13      => current_l1id,       --32
    probe14      => last_l1id          --32
 
);
 
 
end RTL;