onehot_dec.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.02.2017 11:16:21
-- Design Name: 
-- Module Name: onehot_dec 
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
-- n to m decoder 
-- n is number of binary inputs
-- m is the number of one-hot outputs
 
 
 
entity onehot_dec is
--    generic (n : integer := 4; m : integer := 16);
    generic (n : integer := 5; m : integer := 32);
    Port ( bin_in : in STD_LOGIC_VECTOR (n-1 downto 0);
           oh_out : out STD_LOGIC_VECTOR (m-1 downto 0));
end onehot_dec;
 
architecture RTL of onehot_dec is
 
signal one : unsigned(m-1 downto 0);
signal shift : integer; 
 
begin
 
one  <= to_unsigned(1,m);
shift <= to_integer(unsigned(bin_in));
oh_out <= std_logic_vector(one sll shift);
 
end RTL;