pkt_capture_regs.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
--library unisim;
--use unisim.vcomponents.all;
use work.ipbus.all;
use work.ipbus_decode_L1CaloHubRodPktCaptureRegisters.all;
 
 
 
entity pkt_capture_regs is 
     generic (
        packet_version    : std_logic_vector(2 downto 0)    := "001";
        sim              : integer    := 0; 
        debug            : integer    := 1
        ); 
    Port ( 
 
        ipb_clk            : in std_logic;
        ipb_rst            : in std_logic;
        ipb_in             : in ipb_wbus;
        ipb_out            : out ipb_rbus;  
        pp_clock           : in std_logic;
        full_mode_stat    : in  STD_LOGIC_VECTOR (31 downto 0);
        m_tdata           : in  STD_LOGIC_VECTOR (63 downto 0);
        m_tvalid          : in std_logic;  
        m_tlast           : in std_logic;
        m_header_marker   : in std_logic
        
        );
end pkt_capture_regs;
architecture RTL of pkt_capture_regs is 
 
COMPONENT pkt_capture_ila
 
PORT (
    clk : IN STD_LOGIC;
    probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); 
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
    probe7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
    probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
    probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    probe10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT  ;
 
 
 
signal version                : std_logic_vector(3 downto 0);
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal capture_control_reg_rst : std_logic;
signal capture_control_reg_stb : std_logic;
signal pkt_capture_control     : std_logic_vector(31 downto 0);
 
signal clear                   : std_logic;
signal clear_s                 : std_logic;
signal clear_s_del             : std_logic;
signal armed                   : std_logic;
signal armed_s                 : std_logic;
signal armed_s_del             : std_logic;
signal armed_pulse             : std_logic;
signal armed_stat              : std_logic;
signal triggered               : std_logic;
signal capture                 : std_logic; 
signal tvalid_prev             : std_logic;
signal l_header_marker         : std_logic;     --replaces m_header_marker input 
 
signal m_header_marker_2       : std_logic; 
signal header_0                : std_logic_vector(63 downto 0);
signal header_0_i              : std_logic_vector(31 downto 0);
signal header_2                : std_logic_vector(31 downto 0);
signal trailer                 : std_logic_vector(63 downto 0);
signal header_1                : std_logic_vector(31 downto 0);
signal trailer_1               : std_logic_vector(31 downto 0);
 
signal incomp_pkt              : std_logic;
signal capture_status          : std_logic_vector(31 downto 0);
 
signal pkt_count               : std_logic_vector(31 downto 0);
 
 
 
begin   
 
fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
   ipb_in => ipb_in,
   ipb_out => ipb_out,
 
    sel => ipbus_sel_L1CaloHubRodPktCaptureRegisters(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
no_sim_regs: if SIM=0 generate 
 
--pulse reg for arming the capture mech -----
Capture_Control_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => capture_control_reg_rst,
          ipbus_in => ipbw(N_SLV_PKT_CAPTURE_CONTROL),
          ipbus_out => ipbr(N_SLV_PKT_CAPTURE_CONTROL),
          stb(0) => capture_control_reg_stb,
          q(0) => pkt_capture_control
        );
capture_control_reg_rst <=  capture_control_reg_stb or ipb_rst;  
 
Capture_status_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_PKT_CAPTURE_STATUS),
          ipb_out => ipbr(N_SLV_PKT_CAPTURE_STATUS),
          slv_clk => pp_clock,
          d(0) => capture_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
Header_0_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_HEADER_0),
          ipb_out => ipbr(N_SLV_HEADER_0),
          slv_clk => pp_clock,
          d(0) => header_0(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
--header_0_i <= "000" & header_0(28 downto 0);  --blank out "version" field
 
 
Header_1_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_HEADER_1),
          ipb_out => ipbr(N_SLV_HEADER_1),
          slv_clk => pp_clock,
          d(0) => header_0(63 downto 32),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
Header_2_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_HEADER_2),
          ipb_out => ipbr(N_SLV_HEADER_2),
          slv_clk => pp_clock,
          d(0) => header_2(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
trailer_0_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRAILER_0),
          ipb_out => ipbr(N_SLV_TRAILER_0),
          slv_clk => pp_clock,
          d(0) => trailer(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
trailer_1_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRAILER_1),
          ipb_out => ipbr(N_SLV_TRAILER_1),
          slv_clk => pp_clock,
          d(0) => trailer(63 downto 32),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
pkt_count_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_PKT_COUNT),
          ipb_out => ipbr(N_SLV_PKT_COUNT),
          slv_clk => pp_clock,
          d(0) => pkt_count,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
end generate no_sim_regs; 
 
header_0_i <= header_0(31 downto 0);  
 
-----capture mech -------------------
 
-------sample the pulse reg in the pp_clock domain ------
--armed_s samples the pulse bit running on ipb_clk
--armed_s_del sample armed_s synchronously on pp_clock
--armed_stat is the user's status flag indicating the mech is armed, but not triggered
 
--clear <= pkt_capture_control(1);
 
--clear pulse happens on trailing edge of ipbus pulse 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     clear_s <= pkt_capture_control(1);
     clear_s_del <= clear_s; 
  end if;   
end process;
 
clear <= clear_s_del and not clear_s;
 
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     armed_s <= pkt_capture_control(0);
     armed_s_del <= armed_s; 
  end if;   
end process;
 
armed_pulse <= armed_s_del and not armed_s;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     if (ipb_rst = '1') or (capture = '1') or (clear = '1') then
       armed_stat <= '0';
     elsif (armed_pulse = '1') then 
       armed_stat <= '1';         
     else 
       armed_stat <= armed_stat;     
     end if;  
  end if;
end process;
 
 
--The header marker coming from the TOB processor is not currently reliable, so a stand alone version is created here 
process (pp_clock) begin
    if rising_edge (pp_clock) then
       if (ipb_rst = '1') or (clear = '1') then
          tvalid_prev <= '0';
       else
          tvalid_prev <= (not m_tvalid) or (m_tlast and m_tvalid);
       end if;
    end if;
 end process;
 
l_header_marker <= m_tvalid and tvalid_prev and not m_tlast;  --packets should be at least two 64-bit words (header and trailer) 
 
 
 
 
-- Capture - active during the event being captured and then cleared --  
process(pp_clock) begin
  if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
          capture <= '0';
      elsif (armed_stat = '1') and (l_header_marker = '1') then 
          capture <= '1'; 
      elsif (capture = '1') and (m_tlast = '1') then 
          capture <= '0';
      else 
          capture <= capture;          
      end if;
   end if;    
end process;          
 
-- triggered - status bit to indicate an event has been captured 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
         triggered <= '0';            
      elsif (capture = '1') then 
          triggered <= '1';
      elsif (armed_pulse = '1') then 
          triggered <= '0';
      else 
          triggered <= triggered;                
      end if; 
   end if;    
end process;
 
-- capture the header 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if  (clear = '1') then 
             header_0 <= (others => '0');
      elsif (armed_stat = '1' ) and (l_header_marker = '1') then 
             header_0 <= m_tdata; 
      else 
          header_0 <= header_0;    
      end if; 
   end if;
end process;           
          
--make an enable for capturing the second header word
process(pp_clock) begin
   if rising_edge (pp_clock) then
      m_header_marker_2 <= l_header_marker;
   end if;   
end process; 
 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if  (clear = '1') then 
           header_2 <= (others => '0');
      elsif (capture = '1' ) and (m_header_marker_2 = '1') then 
          header_2 <= m_tdata(31 downto 0); 
      else
          header_2 <= header_2;    
      end if; 
   end if;
end process;
 
--capture trailer 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (clear = '1') then 
          trailer <= (others => '0');
      elsif  (capture = '1' ) and (m_tlast = '1') then 
          trailer <= m_tdata;
      else 
          trailer <= trailer;     
      end if; 
   end if;
end process;
 
 
--incomp_pkt is active while capture is active:   
incomp_pkt <= capture;
 
 
capture_status <=  '0' & packet_version & x"000000"  & '0'  & incomp_pkt & triggered  & armed_stat;
 
--packet counter  
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
          pkt_count <= (others => '0');
      elsif  (m_tlast = '1') and (m_tvalid = '1') then 
          pkt_count  <= (pkt_count + 1);
      else 
          pkt_count <= pkt_count;     
      end if; 
   end if;
end process;
 
--pkt_capture_probe : pkt_capture_ila 
--  Port map  (
--   clk    => pp_clock,
--   probe0(0) => m_tvalid,         -- 1-bit
--   probe1(0) => m_tlast,          -- 1-bit
--   probe2    => m_tdata,          -- 64-bits
--   probe3(0) => l_header_marker,    -- 1-bit
--   probe4(0) => m_header_marker_2,  -- 1-bit
--   probe5(0) => capture,            -- 1-bit
--   probe6    => header_0(31 downto 0), -- 32-bit
--   probe7    => header_1,
--   probe8    => header_2(31 downto 0),
--   probe9    => trailer(31 downto 0),
--   probe10   => trailer_1,
--   probe11(0)   => m_header_marker
--   );
   
--   header_1 <= header_0(63 downto 32);
--   trailer_1 <= trailer(63 downto 32);
 
end RTL;