reset_count.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.02.2019 13:36:52
-- Design Name: 
-- Module Name: reset_count - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity reset_count is
  generic
(
 COUNTER_WIDTH  : integer :=   5       
 
);    
 
    Port ( 
               clock : in STD_LOGIC;
               power_down_b: out STD_LOGIC
               );
end reset_count;
 
architecture RTL of reset_count is
 
signal counter :  std_logic_vector(counter_width-1 downto 0) := (others => '0');
signal count_max : STD_LOGIC_VECTOR (counter_width-1 downto 0) := (others => '1');
signal done     : std_logic := '0';
 
begin
 
count_max <= (others => '1');
 
process (clock) begin 
  if rising_edge (clock) then 
    if counter = count_max then
       counter <= counter;
       done <='1';
    else  
        counter <= counter +1;  
    end if; 
  end if; 
end process;      
 
power_down_b <= done;
 
 
end RTL;