threshold_counter.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 15.04.2019 13:30:11
-- Design Name: 
-- Module Name: threshold_counter - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.2 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--This is an "above threshold counter" for the input fifos.   When the fifo level is above the set threshold, the counter increments
--until it saturates at all ones.   The counter is clocked at 40MHz 
 
entity threshold_counter is
    Port ( 
    clock       : in STD_LOGIC;
    reset       : in STD_LOGIC;                      --async reset (ipb_clock sync from reg)
--    time_count  : in STD_LOGIC;
    threshold   : in STD_LOGIC_VECTOR(15 downto 0);  --synchronous to ipb_clock, but not a risk because counter reset should follow writing 
    level       : in STD_LOGIC_VECTOR(15 downto 0);   --synchronous to pp_clock from the slave side o fthe fifo  
    above_count : out STD_LOGIC_VECTOR(31 downto 0);
    
    busy        : out STD_LOGIC
        
    );
end threshold_counter;
 
architecture RTL of threshold_counter is
 
signal  above_counter : std_logic_vector(31 downto 0);
signal  busy_i        : std_logic; 
 
begin
 
process(clock, reset)
    begin
        if reset = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
            above_counter <= (others => '0');
        elsif rising_edge(clock) then
            if (level > threshold) and (above_counter < x"ffff_ffff") then 
              above_counter <= (above_counter + 1);
            else 
              above_counter <= above_counter; 
            end if; 
        end if; 
 end process;
 
 above_count(31 downto 0) <= above_counter(31 downto 0);   --two lsb's are ignored because the clock is 160MHz and the count rate is 40MHz 
 
 
 ---busy generation with hysterisis ------
 
 
 
 process(clock, reset)
    begin
        if reset = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
            busy_i <=  '0';
        elsif rising_edge(clock) then
            if busy_i = '0' then 
                if (level > threshold) then --formerly threshold + 2
                    busy_i <= '1';
                 else busy_i <= busy_i;
                 end if;
            elsif busy_i = '1' then
                  if (level < threshold - 16) then --formerly threshold - 2
                    busy_i <= '0';
                  else busy_i <= busy_i;
                  end if;
            end if;      
          else busy_i <= busy_i;                        
     --       end if; 
        end if; 
 end process;
 
 busy <= busy_i;
 
end RTL;