tob_rx_timer.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 22.04.2022 15:09:38
-- Design Name: 
-- Module Name: tob_rx_timer - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity tob_rx_timer is
    Port ( 
           pp_clock :   in  STD_LOGIC;
           L1A      :   in STD_LOGIC;
           s_tvalid :   in STD_LOGIC;
           reset    :   in STD_LOGIC;
           tob_rx_time :  out std_logic_vector(15 downto 0);
           tob_rx_time_max :  out std_logic_vector(15 downto 0)
           );
           
           
                   
end tob_rx_timer;
 
architecture RTL of tob_rx_timer is
 
signal  time_count  :  std_logic_vector(15 downto 0):= x"0000";
signal  stop        :  std_logic;
signal  tob_rx_time_i :  std_logic_vector(15 downto 0):= x"0000";
signal  tob_rx_time_max_i :  std_logic_vector(15 downto 0) := x"0000";
 
begin
 
     
process(pp_clock, L1A)
    begin
        if (L1A = '1') or (reset = '1') then                     -- async (p)reset -> put 'reset in sensitivity list
            time_count <= (others => '0');
            stop <= '0';
        elsif rising_edge(pp_clock) then 
            if s_tvalid = '0' and (stop = '0') then 
              time_count <= (time_count + 1); 
            elsif s_tvalid = '1' then 
               stop <= '1'; 
               time_count <= time_count;
            else 
               stop <= stop; 
               time_count <= time_count; 
            end if;        
        end if; 
 end process;
 
process(pp_clock)
    begin
       if rising_edge(pp_clock) then 
          if reset = '1' then 
             tob_rx_time_i <= (others => '0');
          elsif stop = '1' then 
             tob_rx_time_i <= time_count;
          else 
             tob_rx_time_i <= tob_rx_time_i;
          end if;         
       end if; 
end process;          
 
process(pp_clock)
    begin
       if rising_edge(pp_clock) then 
          if (reset = '1') then 
             tob_rx_time_max_i <= (others => '0');          
          elsif stop = '1' then 
            if tob_rx_time_i > tob_rx_time_max_i then 
               tob_rx_time_max_i <= tob_rx_time_i;
            else 
               tob_rx_time_max_i <=   tob_rx_time_max_i;
            end if;
          else        
               tob_rx_time_max_i <=   tob_rx_time_max_i;
          end if; 
        end if;        
 end process; 
 
    
             
tob_rx_time <= tob_rx_time_i;
tob_rx_time_max <= tob_rx_time_max_i;
 
end RTL;