tob_timeout.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.01.2021 14:07:05
-- Design Name: 
-- Module Name: tob_timeout - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
--This block is used in the TOB processor.  After an L1A is received, 
-->This block takes in a programmable time from a register (time_set).  
-->The timer is started counting from zero by a 1 cycle pulse on the "start" input. 
-->The timer is stopped, set to zero, and timeout set to 0 by a 1 cycle pulse on the "stop" input or reset. 
-->If the counter reaches the set_time value, timeout is set to '1' and the counter is stopped. 
 
-->when the timer reaches the programmed time
 
--> The counter has now been extended to 18-bits in order to give it twice the available time.  
--The external connections are still 16 bits, giving the impression that it is counting at 1/2 
--the previous rate (pp_clock/2 = 100MHz) 
 
entity tob_timeout is
   generic ( 
           counter_width                  :  integer    := 19;
           msb                            :  integer    := (counter_width - 1);
           lsb                            :  integer    := (counter_width - 16)
           ); 
 
    Port ( clock     : in STD_LOGIC;
           reset        : in STD_LOGIC;
           start_timer  : in STD_LOGIC;
           stop_timer   : in STD_LOGIC;
           set_time_1   : in STD_LOGIC_VECTOR(15 downto 0);
           set_time_n   : in STD_LOGIC_VECTOR(15 downto 0);
           timeout_1    : out STD_LOGIC;
           timeout_n    : out STD_LOGIC;
           counter_out  : out STD_LOGIC_VECTOR(15 downto 0);
           run_out      : out STD_LOGIC            
           );
end tob_timeout;
 
architecture RTL of tob_timeout is
 
signal counter      :  std_logic_vector(msb downto 0) := (others => '0');
signal run          : std_logic := '0';
signal timeout_1_i    : STD_LOGIC;
signal timeout_n_i    : STD_LOGIC;  
 
begin
 
 
process (clock) begin 
  if rising_edge (clock) then 
    if (reset = '1') or (stop_timer = '1') then 
      counter <= (others => '0');
      run <=  '0';
    elsif  (start_timer = '1')  then
      run <= '1';
      counter <= (others => '0');        
    elsif (counter(msb downto lsb) >= set_time_1) and (counter(msb downto lsb) >= set_time_n)  then
       counter <= counter;
       run  <= '0';
    elsif  (run = '1')  then 
      counter <= counter +1;          
    else  
        counter <= counter;  
    end if; 
  end if; 
end process;      
 
process (clock) begin 
  if rising_edge (clock) then 
    if (reset = '1') or (stop_timer = '1') or (start_timer = '1') then 
       timeout_1_i <= '0'; 
       timeout_n_i <= '0'; 
    elsif  counter(msb downto lsb) >= set_time_1  then 
       timeout_1_i <= '1';
    elsif  counter(msb downto lsb) >= set_time_n  then   
       timeout_n_i <= '1';
    else 
       timeout_1_i <= timeout_1_i; 
       timeout_n_i <= timeout_n_i;  
    end if;
  end if;
end process;     
 
 timeout_1 <= timeout_1_i;   
 timeout_n <= timeout_n_i;
 counter_out <= counter(msb downto lsb); 
 run_out <= run;
          
end RTL;