top_rod_efex.vhd File Reference

This is the top level of the ROD_eFEX FPGA firmware. More...

Go to the source code of this file.

Entities
top_rod_efex	entity
rtl	architecture

Detailed Description

This is the top level of the ROD_eFEX FPGA firmware.

Overview

This firmware image is compatible with the eFEX shelves. The top level ROD has 4 major components as described below

ROD_system

The ROD system includes the following functional blocks:
-ethernet interface, -IPBUS control infrastructure, -AXI4 subsystem block diagram including xilinx peripherals -SPI, I2C, Flach interface, XADC interface, HWICAP

Packet Processor

The Packet Processor consists of the following major blocks: -TOB processor This is the most complex subsystem in the design, responsible for creating the Event Packets It is also responsible for significant levels of error handling.
-Three Bulk Processors which collect and forward Bulk Data packets from up to 4 FEX modules Each of the Processor sub-blocks hass a dedicated Full Mode output interface.

Backplane Interface

For the ROD_eFEX, the Aurora interface consists of 12 four-lane Aurora inputs. In addition the Backplane Interface contains the physical layer interfaces for Combined TTC receiver and Readout_Control Transmitter. -Aurora Interface -Readout Control -Combined TTC

Output Staging FIFOS

There is an output staging fifo between each processor output and its Full Mode interface. These fifos can accumulate output data during times of several back-to-back events or while Felix backpressure is activated.

Output Interfaces

The output interfaces implement the Felix Full Mode protocol. The design incorporates an example design published by the Felix team.

-Felix full mode

Author

Ed Flaherty

Definition in file top_rod_efex.vhd.