ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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top_rod_efex.vhd
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1 
37 library IEEE;
38 use IEEE.STD_LOGIC_1164.ALL;
39 
40 library unisim;
41 use unisim.vcomponents.all;
42 use work.ipbus.ALL;
43 
44 entity top_rod_efex is
45  generic (
46  Module_ID : std_logic_vector (31 downto 0) := x"400000ED";
47  --bit31: reserved
48  --bit30: rod_efex
49  --bit29: rod_jfex
50  --bit28: golden image
51 
52  -- pcbUpdate = x"4" --this is stored in NOVO memory, but any board in circulation will be rev 4
53  -- issue = x"0" -- not defined today
54  -- serial = x"00" --this is stored in the novo ram so perhaps this should be read from there via software
55  -- L1CaloNumber = x"0ed0" --this is a made up number
56  -- module id = x"400000ed"
59  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"20200909";
61  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000001";
63  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000002";
65  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000003";
67  TOP_VER : std_logic_vector(31 downto 0) := x"00000004";
69  TOP_SHA : std_logic_vector(31 downto 0) := x"00000005";
70  CON_VER : std_logic_vector(31 downto 0) := x"00000006";
72  CON_SHA : std_logic_vector(31 downto 0) := x"00000007";
73  HOG_VER : std_logic_vector(31 downto 0) := x"00000008";
75  HOG_SHA : std_logic_vector(31 downto 0) := x"00000009";
76 
77  --IPBus XML
79  XML_SHA : std_logic_vector(31 downto 0) := x"0000000a";
81  XML_VER : std_logic_vector(31 downto 0) := x"0000000b";
82 
84  ROD_EFEX_SHA : std_logic_vector(31 downto 0) := x"0000000c";
85  ROD_EFEX_VER : std_logic_vector(31 downto 0) := x"0000000d";
86 
87 -- CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; --old poly
88  CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8359f"; --correct poly
89  jfex_rod : integer := 0;
90  efex_rod : integer := 1;
91  golden_rod : integer := 0;
92 
93  tob_0_flx_bp_link : integer := 0;
94  bulk_0_flx_bp_link : integer := 1;
95  bulk_1_flx_bp_link : integer := 2;
96  bulk_2_flx_bp_link : integer := 3;
97  debug : integer := 0;
98  alt_cttc : integer := 1;
99 
100 -- XmlVersion : std_logic_vector (31 downto 0) := x"20200309";
101 -- BuildTimeAndDate : std_logic_vector (31 downto 0) := x"20200415";
102 -- FirmwareVersion : std_logic_vector (31 downto 0) := x"20200415";
103  -- User parameters ends
104  -- Do not modify the parameters beyond this line
105 
106  -- Width of S_AXI data bus
107  C_S_AXI_DATA_WIDTH : integer := 32;
108  -- Width of S_AXI address bus
109  C_S_AXI_ADDR_WIDTH : integer := 9
110  );
111 
112  port (
113 
114 -- ipbus system ports
115 
116  CLK_125_pin : in std_logic;
117  CLK_40_pin_P : in std_logic;
118  CLK_40_pin_N : in std_logic;
119 
120  -- 125 MHZ clock output from MMCM to test pin
121  gtx_clk_bufg_out : out std_logic;
122  phy_resetn : out std_logic;
123 
124  -- RGMII Interface
125  ------------------
126  rgmii_txd : out std_logic_vector(3 downto 0);
127  rgmii_tx_ctl : out std_logic;
128  rgmii_txc : out std_logic;
129  rgmii_rxd : in std_logic_vector(3 downto 0);
130  rgmii_rx_ctl : in std_logic;
131  rgmii_rxc : in std_logic;
132 
133  -- MDIO Interface
134  -----------------
135  mdio : inout std_logic;
136  mdc : out std_logic;
137  reset_error : in std_logic;
138 
139  --LEDs
140  -----------------
141  leds : out std_logic_vector(1 downto 0);
142  userled : out std_logic;
143  rotary_switch : in std_logic_vector(3 downto 0);
144 -- geo_location : in std_logic_vector(7 downto 0);
145 
146  -- GPIO Interface
147  -------------------
148  gp_button : in std_logic;
149 -- test1_2 : in std_logic;
150 -- test1_3 : in std_logic;
151 -- test1_4 : in std_logic;
152 -- test1_5 : in std_logic;
153  t_wrn_b : in std_logic;
154  smbalert_b : in std_logic;
155  -- gpio2_tri_i(7) => ,
156  -- gpio2_tri_i(8) => ,
157  ck_pll_lock : in std_logic;
158  ck_int : in std_logic;
159  phy_int : in std_logic;
160  t_pod0_int : in std_logic;
161  t_pod1_int : in std_logic;
162  t_pod2_int : in std_logic;
163  r_pod_int : in std_logic;
164  loc_addr1 : in std_logic;
165  loc_addr2 : in std_logic;
166  loc_addr3 : in std_logic;
167  loc_addr4 : in std_logic;
168  loc_addr5 : in std_logic;
169  loc_addr6 : in std_logic;
170  loc_addr7 : in std_logic;
171  loc_addr8 : in std_logic;
172 
173  lemo : out std_logic;
174 
175 
176  t_pod0_rst_b : out std_logic;
177  t_pod1_rst_b : out std_logic;
178  t_pod2_rst_b : out std_logic;
179  r_pod_rst_b : out std_logic;
180 
181  --Configuration Flash Interface
182  ---------------------------------
183  EMC_INTF_addr : out STD_LOGIC_VECTOR ( 28 downto 0 );
184  EMC_INTF_ce_n : out STD_LOGIC_VECTOR ( 0 to 0 );
185  EMC_INTF_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
186  EMC_INTF_wen : out STD_LOGIC;
187  emc_intf_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
188 
189  --I2C 1,0 interface
190  ----------------------------------
191  iic_1_scl_io : inout STD_LOGIC;
192  iic_1_sda_io : inout STD_LOGIC;
193  iic_scl_io : inout STD_LOGIC;
194  iic_sda_io : inout STD_LOGIC;
195 
196  --SPI Interface
197  ------------------------------------
198  CK_SPI_MOSI : inout STD_LOGIC; --MOSI
199  CK_SPI_MISO : inout STD_LOGIC; --MISO
200  CK_SPI_CK : inout STD_LOGIC;
201  CK_SPI_LE : out STD_LOGIC;
202 
203  --XADC interface
204  --------------------------------------
205  Vp_Vn_v_n : in STD_LOGIC;
206  Vp_Vn_v_p : in STD_LOGIC;
207 
208 
209 -- -----------------------------------------------------------------
210 -- -- backplane interfce --
211 -- ------------------------------------------------------------------
212 --GT ref clocks
213  GTCLK_q112_c0p : in STD_LOGIC;
214  GTCLK_q112_c0n : in STD_LOGIC;
215 
216  GTCLK_q115_c0p : in STD_LOGIC;
217  GTCLK_q115_c0n : in STD_LOGIC;
218 
219  GTCLK_q118_c0p : in STD_LOGIC;
220  GTCLK_q118_c0n : in STD_LOGIC;
221 
222  GTCLK_q211_c0p : in STD_LOGIC;
223  GTCLK_q211_c0n : in STD_LOGIC;
224 
225  GTCLK_q214_c0p : in STD_LOGIC;
226  GTCLK_q214_c0n : in STD_LOGIC;
227 
228  GTCLK_q217_c0p : in STD_LOGIC;
229  GTCLK_q217_c0n : in STD_LOGIC;
230 
231 -- GTCLK_q218_c0p : in STD_LOGIC;
232 -- GTCLK_q218_c0n : in STD_LOGIC;
233 
234  GTCLK_q219_c0p : in STD_LOGIC;
235  GTCLK_q219_c0n : in STD_LOGIC;
236 
237 
238  GTCLK_q218_c1p : in STD_LOGIC;
239  GTCLK_q218_c1n : in STD_LOGIC;
240 
241 -- GTCLK_q118_c1p : in STD_LOGIC;
242 -- GTCLK_q118_c1n : in STD_LOGIC;
243 
244 -- GTCLK_q111_c1p : in STD_LOGIC;
245 -- GTCLK_q111_c1n : in STD_LOGIC;
246 
247 
248 
249  -----aurora slot 3 ----------------
250  RXP_3 : in STD_LOGIC_VECTOR (0 to 3);
251  RXN_3 : in STD_LOGIC_VECTOR (0 to 3);
252  -----aurora slot 4 ----------------
253  RXP_4 : in STD_LOGIC_VECTOR (0 to 3);
254  RXN_4 : in STD_LOGIC_VECTOR (0 to 3);
255  -----aurora slot 5 ----------------
256  RXP_5 : in STD_LOGIC_VECTOR (0 to 3);
257  RXN_5 : in STD_LOGIC_VECTOR (0 to 3);
258  -----aurora slot 6 ----------------
259  RXP_6 : in STD_LOGIC_VECTOR (0 to 3);
260  RXN_6 : in STD_LOGIC_VECTOR (0 to 3);
261  -----aurora slot 7 ----------------
262  RXP_7 : in STD_LOGIC_VECTOR (0 to 3);
263  RXN_7 : in STD_LOGIC_VECTOR (0 to 3);
264  -----aurora slot 8 ----------------
265  RXP_8 : in STD_LOGIC_VECTOR (0 to 3);
266  RXN_8 : in STD_LOGIC_VECTOR (0 to 3);
267  -----aurora slot 9 ----------------
268  RXP_9 : in STD_LOGIC_VECTOR (0 to 3);
269  RXN_9 : in STD_LOGIC_VECTOR (0 to 3);
270  -----aurora slot 10 ----------------
271  RXP_10 : in STD_LOGIC_VECTOR (0 to 3);
272  RXN_10 : in STD_LOGIC_VECTOR (0 to 3);
273  -----aurora slot 11 ----------------
274  RXP_11 : in STD_LOGIC_VECTOR (0 to 3);
275  RXN_11 : in STD_LOGIC_VECTOR (0 to 3);
276  -----aurora slot 12 ----------------
277  RXP_12 : in STD_LOGIC_VECTOR (0 to 3);
278  RXN_12 : in STD_LOGIC_VECTOR (0 to 3);
279  -----aurora slot 13 ----------------
280  RXP_13 : in STD_LOGIC_VECTOR (0 to 3);
281  RXN_13 : in STD_LOGIC_VECTOR (0 to 3);
282  -----aurora slot 14 ----------------
283  RXP_14 : in STD_LOGIC_VECTOR (0 to 3);
284  RXN_14 : in STD_LOGIC_VECTOR (0 to 3);
285 
286  ------------------------------------------------
287 
288 
289 
290 
291 
292  ----readout_ctrl specific
293 
294  RO_CTRL_TXN : out std_logic;
295  RO_CTRL_TXP : out std_logic;
296 
297 -- DRP_CLK_IN : in std_logic
298 -- DRP_CLK_IN_P : in std_logic;
299 -- DRP_CLK_IN_N : in std_logic
300 
301  --combined_ttc
302 
303  RXP_ttc : in std_logic;
304  RXN_ttc : in std_logic;
305 
306  CTTC_rxp_alt : in std_logic;
307  CTTC_rxn_alt : in std_logic;
308 --Full Mode Interface
309 
310 
311 
312 
313 --first full mode interface (2-channel in quad shared with Aurora)
314  fm1_gttxn_out : out std_logic_vector(1 downto 0);
315  fm1_gttxp_out : out std_logic_vector(1 downto 0);
316 
317 
318 --second full mode interface (2-channel in quad shared with Aurora)
319  fm2_gttxn_out : out std_logic_vector(1 downto 0);
320  fm2_gttxp_out : out std_logic_vector(1 downto 0);
321 
322 
323 
324 -- CLK_40 : in STD_LOGIC
325  ----board tieoff signals
326  CK_PWR_DNB : out std_logic;
327  REF_CLK_SEL : out std_logic;
328  CK_SYNCB : out std_logic;
329  PWR_CON3 : out std_logic;
330  PWR_CON4 : out std_logic
331 -- these are also buried in the GPIO pins and constraints.
332 -- SPI_LE : out std_logic;
333 -- TPOD1_RST : out std_logic;
334 -- TPOD2_RST : out std_logic;
335 -- TPOD3_RST : out std_logic;
336 -- RPOD_RST : out std_logic
337 
338 -- LED3 : out std_logic
339 
340 
341 
342 
343 
344 
345 --EF pkt_clk used for accessing the packet processor registers synchronously
346 -- PKT_CLK : in STD_LOGIC;
347 --EF reset signal for packet_proc clock domain
348 -- pkt_ARESETN : in STD_LOGIC
349 
350 
351  );
352 end top_rod_efex;
353 
354 architecture rtl of top_rod_efex is
355 
356  COMPONENT bkpln_control_ila
357 
358  PORT (
359  clk : IN STD_LOGIC;
360  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
361  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
362  probe2 : IN STD_LOGIC_VECTOR(31 downto 0)
363  );
364 END COMPONENT ;
365 
366 
367  component packet_processor_clock
368  port
369  (-- Clock in ports
370  -- Clock out ports
371  pp_clock : out std_logic;
372  rt_clock : out std_logic;
373  -- Status and control signals
374  locked : out std_logic;
375  clk_in1 : in std_logic
376  );
377  end component;
378 
379 
380  component ROD_system
381  generic (
382  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"20201005";
383  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000001";
384  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000002";
385  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000003";
386  TOP_VER : std_logic_vector(31 downto 0) := x"00000004";
387  TOP_SHA : std_logic_vector(31 downto 0) := x"00000005";
388  CON_VER : std_logic_vector(31 downto 0) := x"00000006";
389  CON_SHA : std_logic_vector(31 downto 0) := x"00000007";
390  HOG_VER : std_logic_vector(31 downto 0) := x"00000008";
391  HOG_SHA : std_logic_vector(31 downto 0) := x"00000009";
392 
393  --IPBus XML
394  XML_SHA : std_logic_vector(31 downto 0) := x"0000000a";
395  XML_VER : std_logic_vector(31 downto 0) := x"0000000b";
396 
397  ROD_EFEX_SHA : std_logic_vector(31 downto 0) := x"0000000c";
398  ROD_EFEX_VER : std_logic_vector(31 downto 0) := x"0000000d";
399 
400  jfex_rod : integer := 0;
401  efex_rod : integer := 0;
402  golden_rod : integer := 0;
403 
404  -----------------------------------------
405  Module_ID : std_logic_vector (31 downto 0) := x"00000001";
406 -- XmlVersion : std_logic_vector (31 downto 0) := x"00000002";
407  BuildTimeAndDate : std_logic_vector (31 downto 0) := x"00000003";
408  FirmwareVersion : std_logic_vector (31 downto 0) := x"00000004"
409  );
410 
411  port (
412  ipbr_backplane: in ipb_rbus;
413  ipbw_backplane: out ipb_wbus;
414  ipbr_Processor: in ipb_rbus;
415  ipbw_Processor: out ipb_wbus;
416  ipb_clk : out std_logic;
417  ipb_rst : out std_logic;
418 
419  rotary_switch : in std_logic_vector(3 downto 0);
420  CLK_125 : in std_logic;
421  gtx_clk_bufg_out : out std_logic;
422 
423 
424  phy_resetn : out std_logic;
425 
426  -- RGMII Interface
427  ------------------
428  rgmii_txd : out std_logic_vector(3 downto 0);
429  rgmii_tx_ctl : out std_logic;
430  rgmii_txc : out std_logic;
431  rgmii_rxd : in std_logic_vector(3 downto 0);
432  rgmii_rx_ctl : in std_logic;
433  rgmii_rxc : in std_logic;
434 
435  -- MDIO Interface
436  -----------------
437  mdio : inout std_logic;
438  mdc : out std_logic;
439  reset_error : in std_logic;
440 
441  --LEDs
442  -----------------
443  leds : out std_logic_vector(1 downto 0);
444  userled : out std_logic;
445 
446  -- GPIO Interface
447  -------------------
448  gp_button : in std_logic;
449  test1_2 : in std_logic;
450  test1_3 : in std_logic;
451  test1_4 : in std_logic;
452  test1_5 : in std_logic;
453  t_wrn_b : in std_logic;
454  smbalert_b : in std_logic;
455  -- gpio2_tri_i(7) => ,
456  -- gpio2_tri_i(8) => ,
457  ck_pll_lock : in std_logic;
458  ck_int : in std_logic;
459  phy_int : in std_logic;
460  t_pod0_int : in std_logic;
461  t_pod1_int : in std_logic;
462  t_pod2_int : in std_logic;
463  r_pod_int : in std_logic;
464  loc_addr1 : in std_logic;
465  loc_addr2 : in std_logic;
466  loc_addr3 : in std_logic;
467  loc_addr4 : in std_logic;
468  loc_addr5 : in std_logic;
469  loc_addr6 : in std_logic;
470  loc_addr7 : in std_logic;
471  loc_addr8 : in std_logic;
472 
473 -- rod_gp_led : out std_logic;
474 -- FP_GP_LED_B : out std_logic;
475  FP_RUN_LED_B : out std_logic;
476  lemo : out std_logic;
477  -- gpio_tri_o(4) => ,
478  pwr_con3 : out std_logic;
479  pwr_con4 : out std_logic;
480  -- gpio_tri_o(7) => ,
481  ck_pwr_dnb : out std_logic;
482  ref_clk_sel : out std_logic;
483  ck_syncb : out std_logic;
484 -- phy_rst_n : out std_logic;
485  t_pod0_rst_b : out std_logic;
486  t_pod1_rst_b : out std_logic;
487  t_pod2_rst_b : out std_logic;
488  r_pod_rst_b : out std_logic;
489 
490  --Configuration Flash Interface
491  ---------------------------------
492  EMC_INTF_addr : out STD_LOGIC_VECTOR ( 28 downto 0 );
493  EMC_INTF_ce_n : out STD_LOGIC_VECTOR ( 0 to 0 );
494  EMC_INTF_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
495  EMC_INTF_wen : out STD_LOGIC;
496  emc_intf_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
497 
498  --I2C 1,0 interface
499  ----------------------------------
500  iic_1_scl_io : inout STD_LOGIC;
501  iic_1_sda_io : inout STD_LOGIC;
502  iic_scl_io : inout STD_LOGIC;
503  iic_sda_io : inout STD_LOGIC;
504 
505  --SPI Interface
506  ------------------------------------
507  CK_SPI_MOSI : inout STD_LOGIC; --MOSI
508  CK_SPI_MISO : inout STD_LOGIC; --MISO
509  CK_SPI_CK : inout STD_LOGIC;
510  CK_SPI_LE : inout STD_LOGIC;
511 
512  --XADC interface
513  --------------------------------------
514  Vp_Vn_v_n : in STD_LOGIC;
515  Vp_Vn_v_p : in STD_LOGIC
516 
517 
518 
519  );
520  end component;
521 
522 
523  component aurora_64b_rx_12ch
524  Port (
525 
526  pp_clock : in std_logic;
527  clk_160 : out std_logic;
528  backplane_control : in std_logic_vector(31 downto 0);
529 
530  cttc_cpllpd_in : in STD_LOGIC;
531  cttc_rxbufreset_in : in STD_LOGIC;
532  cttc_rxpcsreset_in : in STD_LOGIC;
533  cttc_rxpmareset_in : in STD_LOGIC;
534  cttc_rxcdrhold_in : in STD_LOGIC;
535  cttc_rxpd_in : in STD_LOGIC;
536 
537  GTCLK_q112_c0p : in STD_LOGIC;
538  GTCLK_q112_c0n : in STD_LOGIC;
539  GTCLK_q115_c0p : in STD_LOGIC;
540  GTCLK_q115_c0n : in STD_LOGIC;
541 
542  GTCLK_q118_c0p : in STD_LOGIC;
543  GTCLK_q118_c0n : in STD_LOGIC;
544 
545  GTCLK_q211_c0p : in STD_LOGIC;
546  GTCLK_q211_c0n : in STD_LOGIC;
547 
548  GTCLK_q214_c0p : in STD_LOGIC;
549  GTCLK_q214_c0n : in STD_LOGIC;
550 
551  GTCLK_q217_c0p : in STD_LOGIC;
552  GTCLK_q217_c0n : in STD_LOGIC;
553 
554 -- CLK_125 : in std_logic;
555  INIT_CLK : in std_logic;
556  GT_RESET_IN : in std_logic;
557  RESET : in std_logic;
558  vio_chan_reset : in std_logic;
559  sys_top_reset : in std_logic;
560 
561 
562 -----aurora ch0 ----------------
563 -----aurora slot 3 ----------------
564  RXP_3 : in STD_LOGIC_VECTOR (0 to 3);
565  RXN_3 : in STD_LOGIC_VECTOR (0 to 3);
566 
567  CHANNEL_STAT_3 : out std_logic_vector(31 downto 0);
568  CHANNEL_CTRL_3 : in std_logic_vector(31 downto 0);
569  m_axi_rx_tdata_3 : out std_logic_vector(63 downto 0);
570  m_axi_rx_tvalid_3 : out std_logic;
571  m_axi_rx_tlast_3 : out std_logic;
572  -- User Flow Control RX Inteface
573  m_axi_ufc_rx_tdata_3 : out std_logic_vector(63 downto 0);
574  m_axi_ufc_rx_tkeep_3 : out std_logic_vector(7 downto 0);
575  m_axi_ufc_rx_tvalid_3 : out std_logic;
576  m_axi_ufc_rx_tlast_3 : out std_logic;
577  USER_CLK_OUT_3 : out std_logic;
578 ------------------------------------------------
579 -- Aurora slot 4 ---------------------
580  RXP_4 : in STD_LOGIC_VECTOR (0 to 3);
581  RXN_4 : in STD_LOGIC_VECTOR (0 to 3);
582  CHANNEL_STAT_4 : out std_logic_vector(31 downto 0);
583  CHANNEL_CTRL_4 : in std_logic_vector(31 downto 0);
584  m_axi_rx_tdata_4 : out std_logic_vector(63 downto 0);
585  m_axi_rx_tkeep_4 : out std_logic_vector(7 downto 0);
586  m_axi_rx_tvalid_4 : out std_logic;
587  m_axi_rx_tlast_4 : out std_logic;
588  -- User Flow Control RX Inteface
589  m_axi_ufc_rx_tdata_4 : out std_logic_vector(63 downto 0);
590 --temp m_axi_ufc_rx_tkeep_4 : out std_logic_vector(7 downto 0);
591  m_axi_ufc_rx_tvalid_4 : out std_logic;
592  m_axi_ufc_rx_tlast_4 : out std_logic;
593  USER_CLK_OUT_4 : out std_logic;
594 
595 
596 
597 
598 ---- Aurora 5 ----------------------
599 -----aurora ch2 (aurora 5) ----------------
600  RXP_5 : in STD_LOGIC_VECTOR (0 to 3);
601  RXN_5 : in STD_LOGIC_VECTOR (0 to 3);
602 
603  CHANNEL_STAT_5 : out std_logic_vector(31 downto 0);
604  CHANNEL_CTRL_5 : in std_logic_vector(31 downto 0);
605  m_axi_rx_tdata_5 : out std_logic_vector(63 downto 0);
606 
607  m_axi_rx_tvalid_5 : out std_logic;
608  m_axi_rx_tlast_5 : out std_logic;
609  -- User Flow Control RX Inteface
610  m_axi_ufc_rx_tdata_5 : out std_logic_vector(63 downto 0);
611 
612  m_axi_ufc_rx_tvalid_5 : out std_logic;
613  m_axi_ufc_rx_tlast_5 : out std_logic;
614  USER_CLK_OUT_5 : out std_logic;
615 
616 
617 
618 
619 
620 ------------------------------------------------------
621 -- Aurora slot 6 ---------------------
622  RXP_6 : in STD_LOGIC_VECTOR (0 to 3);
623  RXN_6 : in STD_LOGIC_VECTOR (0 to 3);
624 
625  CHANNEL_STAT_6 : out std_logic_vector(31 downto 0);
626  CHANNEL_CTRL_6 : in std_logic_vector(31 downto 0);
627  m_axi_rx_tdata_6 : out std_logic_vector(63 downto 0);
628 
629  m_axi_rx_tvalid_6 : out std_logic;
630  m_axi_rx_tlast_6 : out std_logic;
631  -- User Flow Control RX Inteface
632  m_axi_ufc_rx_tdata_6 : out std_logic_vector(63 downto 0);
633 
634  m_axi_ufc_rx_tvalid_6 : out std_logic;
635  m_axi_ufc_rx_tlast_6 : out std_logic;
636  USER_CLK_OUT_6 : out std_logic;
637 
638 --Aurora_7 -------------------------------------------
639  RXP_7 : in STD_LOGIC_VECTOR (0 to 3);
640  RXN_7 : in STD_LOGIC_VECTOR (0 to 3);
641 
642  CHANNEL_STAT_7 : out std_logic_vector(31 downto 0);
643  CHANNEL_CTRL_7 : in std_logic_vector(31 downto 0);
644  m_axi_rx_tdata_7 : out std_logic_vector(63 downto 0);
645  m_axi_rx_tvalid_7 : out std_logic;
646  m_axi_rx_tlast_7 : out std_logic;
647  -- User Flow Control RX Inteface
648  m_axi_ufc_rx_tdata_7 : out std_logic_vector(63 downto 0);
649  m_axi_ufc_rx_tvalid_7 : out std_logic;
650  m_axi_ufc_rx_tlast_7 : out std_logic;
651  USER_CLK_OUT_7 : out std_logic;
652 
653 --Aurora_8 -------------------------------------------
654  RXP_8 : in STD_LOGIC_VECTOR (0 to 3);
655  RXN_8 : in STD_LOGIC_VECTOR (0 to 3);
656 
657  CHANNEL_STAT_8 : out std_logic_vector(31 downto 0);
658  CHANNEL_CTRL_8 : in std_logic_vector(31 downto 0);
659  m_axi_rx_tdata_8 : out std_logic_vector(63 downto 0);
660  m_axi_rx_tvalid_8 : out std_logic;
661  m_axi_rx_tlast_8 : out std_logic;
662  -- User Flow Control RX Inteface
663  m_axi_ufc_rx_tdata_8 : out std_logic_vector(63 downto 0);
664  m_axi_ufc_rx_tvalid_8 : out std_logic;
665  m_axi_ufc_rx_tlast_8 : out std_logic;
666  USER_CLK_OUT_8 : out std_logic;
667 
668 
669 --Aurora_9 -------------------------------------------
670  RXP_9 : in STD_LOGIC_VECTOR (0 to 3);
671  RXN_9 : in STD_LOGIC_VECTOR (0 to 3);
672 
673  CHANNEL_STAT_9 : out std_logic_vector(31 downto 0);
674  CHANNEL_CTRL_9 : in std_logic_vector(31 downto 0);
675  m_axi_rx_tdata_9 : out std_logic_vector(63 downto 0);
676  m_axi_rx_tvalid_9 : out std_logic;
677  m_axi_rx_tlast_9 : out std_logic;
678  -- User Flow Control RX Inteface
679  m_axi_ufc_rx_tdata_9 : out std_logic_vector(63 downto 0);
680 
681  m_axi_ufc_rx_tvalid_9 : out std_logic;
682  m_axi_ufc_rx_tlast_9 : out std_logic;
683  USER_CLK_OUT_9 : out std_logic;
684 
685 
686 ---Aurora_10-----------------------------------------
687 
688  RXP_10 : in STD_LOGIC_VECTOR (0 to 3);
689  RXN_10 : in STD_LOGIC_VECTOR (0 to 3);
690 
691  CHANNEL_STAT_10 : out std_logic_vector(31 downto 0);
692  CHANNEL_CTRL_10 : in std_logic_vector(31 downto 0);
693  m_axi_rx_tdata_10 : out std_logic_vector(63 downto 0);
694  m_axi_rx_tvalid_10 : out std_logic;
695  m_axi_rx_tlast_10 : out std_logic;
696  -- User Flow Control RX Inteface
697  m_axi_ufc_rx_tdata_10 : out std_logic_vector(63 downto 0);
698  m_axi_ufc_rx_tvalid_10 : out std_logic;
699  m_axi_ufc_rx_tlast_10 : out std_logic;
700  USER_CLK_OUT_10 : out std_logic;
701 
702 
703 --Aurora_11 -------------------------------------------
704  RXP_11 : in STD_LOGIC_VECTOR (0 to 3);
705  RXN_11 : in STD_LOGIC_VECTOR (0 to 3);
706 
707  CHANNEL_STAT_11 : out std_logic_vector(31 downto 0);
708  CHANNEL_CTRL_11 : in std_logic_vector(31 downto 0);
709  m_axi_rx_tdata_11 : out std_logic_vector(63 downto 0);
710  m_axi_rx_tvalid_11 : out std_logic;
711  m_axi_rx_tlast_11 : out std_logic;
712  -- User Flow Control RX Inteface
713  m_axi_ufc_rx_tdata_11 : out std_logic_vector(63 downto 0);
714 
715  m_axi_ufc_rx_tvalid_11 : out std_logic;
716  m_axi_ufc_rx_tlast_11 : out std_logic;
717 
718  USER_CLK_OUT_11 : out std_logic;
719 
720 
721 
722 ---Aurora_12-----------------------------------------
723 
724  RXP_12 : in STD_LOGIC_VECTOR (0 to 3);
725  RXN_12 : in STD_LOGIC_VECTOR (0 to 3);
726 
727 
728  CHANNEL_STAT_12 : out std_logic_vector(31 downto 0);
729  CHANNEL_CTRL_12 : in std_logic_vector(31 downto 0);
730  m_axi_rx_tdata_12 : out std_logic_vector(63 downto 0);
731 
732  m_axi_rx_tvalid_12 : out std_logic;
733  m_axi_rx_tlast_12 : out std_logic;
734  -- User Flow Control RX Inteface
735  m_axi_ufc_rx_tdata_12 : out std_logic_vector(63 downto 0);
736  m_axi_ufc_rx_tvalid_12 : out std_logic;
737  m_axi_ufc_rx_tlast_12 : out std_logic;
738  USER_CLK_OUT_12 : out std_logic;
739 
740 
741 --Aurora_13 -------------------------------------------
742  RXP_13 : in STD_LOGIC_VECTOR (0 to 3);
743  RXN_13 : in STD_LOGIC_VECTOR (0 to 3);
744 
745  CHANNEL_STAT_13 : out std_logic_vector(31 downto 0);
746  CHANNEL_CTRL_13 : in std_logic_vector(31 downto 0);
747  m_axi_rx_tdata_13 : out std_logic_vector(63 downto 0);
748  m_axi_rx_tvalid_13 : out std_logic;
749  m_axi_rx_tlast_13 : out std_logic;
750  -- User Flow Control RX Inteface
751  m_axi_ufc_rx_tdata_13 : out std_logic_vector(63 downto 0);
752  m_axi_ufc_rx_tvalid_13 : out std_logic;
753  m_axi_ufc_rx_tlast_13 : out std_logic;
754  USER_CLK_OUT_13 : out std_logic;
755 
756 ---Aurora_14-----------------------------------------
757 
758  RXP_14 : in STD_LOGIC_VECTOR (0 to 3);
759  RXN_14 : in STD_LOGIC_VECTOR (0 to 3);
760 
761 
762  CHANNEL_STAT_14 : out std_logic_vector(31 downto 0);
763  CHANNEL_CTRL_14 : in std_logic_vector(31 downto 0);
764  m_axi_rx_tdata_14 : out std_logic_vector(63 downto 0);
765  m_axi_rx_tvalid_14 : out std_logic;
766  m_axi_rx_tlast_14 : out std_logic;
767  -- User Flow Control RX Inteface
768  m_axi_ufc_rx_tdata_14 : out std_logic_vector(63 downto 0);
769  m_axi_ufc_rx_tvalid_14 : out std_logic;
770  m_axi_ufc_rx_tlast_14 : out std_logic;
771  USER_CLK_OUT_14 : out std_logic;
772 
773 ----readout_ctrl specific
774  ro_user_clock : out STD_LOGIC;
775  ro_controller_reset : out STD_LOGIC;
776  ro_txcharisk : in std_logic_vector(3 downto 0);
777  ro_txdata : in std_logic_vector(31 downto 0);
778  ro_status : out std_logic_vector(7 downto 0);
779 
780  RO_CTRL_TXN : out std_logic;
781  RO_CTRL_TXP : out std_logic;
782 
783  DRP_CLK_IN : in std_logic;
784  MASTER_RESET : out std_logic;
785  SW2 : in std_logic;
786 
787 
788 --combined_TTC
789 -- GTCLK_q219_c0p : in std_logic;
790 -- GTCLK_q219_c0n : in std_logic;
791  gt_refclk_q219_c0 : in std_logic;
792  ttc_RXP : in std_logic;
793  ttc_RXN : in std_logic;
794  ttc_word_0 : out std_logic_vector(31 downto 0);
795  ttc_word_1 : out std_logic_vector(31 downto 0);
796  ttc_word_2 : out std_logic_vector(31 downto 0);
797  ttc_word_3 : out std_logic_vector(31 downto 0);
798  ttc_seq : out std_logic_vector(1 downto 0);
799  cttc_usrclk : out std_logic;
800  ttc_reset : in std_logic;
801  ttc_status : out std_logic_vector(31 downto 0);
802 
803  --------------------------ttc MGT ports -----------------------------
804  BP_CTTC_rxdata : out std_logic_vector (31 downto 0);
805  BP_CTTC_rxcharisk : out std_logic_vector (3 downto 0);
806  BP_CTTC_MGT_bus : out STD_LOGIC_VECTOR(31 DOWNTO 0);
807  BP_CTTC_rxoutclk : out std_logic
808 
809 
810  );
811 
812  end component;
813 
814 
815 
816 COMPONENT axi_ch0
817 
818 PORT (
819  clk : IN STD_LOGIC;
820 
821  probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
822  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
823  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
824  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
825  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
826 );
827 END COMPONENT ;
828 
829 COMPONENT ila_full_aurora
830  PORT (
831  clk : IN STD_LOGIC;
832 
833  probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
834  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
835  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
836  probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
837  probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
838  probe5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
839 );
840 END COMPONENT ;
841 
842 component fex_rx_checker
843  Port ( clock : in STD_LOGIC;
844  reset : in STD_LOGIC;
845  tvalid : in STD_LOGIC;
846  tlast : in STD_LOGIC;
847  tdata : in STD_logic_vector(63 downto 0);
848  channel_up : in STD_LOGIC;
849  soft_error : in STD_LOGIC;
850  hard_error : in STD_LOGIC;
851  L1A : in STD_LOGIC;
852  l1id_mis_stretch : in std_logic
853  );
854 end component;
855 
856  component packet_processor
857  generic (
858  CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; --old poly
859  jfex : integer := 0;
860  sim : integer := 0;
861  tob_0_flx_bp_link : integer := 0;
862  bulk_0_flx_bp_link : integer := 1;
863  bulk_1_flx_bp_link : integer := 2;
864  bulk_2_flx_bp_link : integer := 3;
865 
866  -- Width of register file S_AXI data bus
867  C_S_AXI_DATA_WIDTH : integer := 32;
868  -- Width of register file S_AXI address bus
869  C_S_AXI_ADDR_WIDTH : integer := 9;
870  --width of Aurora AXI output
871  bp_width : integer := 64
872  );
873  Port (
874  ipb_clk : in STD_LOGIC;
875  ipb_rst : in STD_LOGIC;
876 -- ipb_in : in ipb_wbus;
877 -- ipb_out : out ipb_rbus;
878  ipb_in_backplane : in ipb_wbus;
879  ipb_out_backplane : out ipb_rbus;
880  ipb_in_processor : in ipb_wbus;
881  ipb_out_processor : out ipb_rbus;
882 
883  geo_location : in STD_LOGIC_VECTOR (7 downto 0);
884  L1A : out std_logic;
885  L1A_delay_out : out std_logic;
886  l1id_mis_stretch : out std_logic;
887  full_mode_stat_tob_0 : in std_logic_vector(31 downto 0);
888  full_mode_stat_bulk_0 : in std_logic_vector(31 downto 0);
889  full_mode_stat_bulk_1 : in std_logic_vector(31 downto 0);
890  full_mode_stat_bulk_2 : in std_logic_vector(31 downto 0);
891  FM_L1id_stat_tob_0 : in std_logic_vector(31 downto 0);
892  FM_L1id_stat_bulk_0 : in std_logic_vector(31 downto 0);
893  FM_L1id_stat_bulk_1 : in std_logic_vector(31 downto 0);
894  FM_L1id_stat_bulk_2 : in std_logic_vector(31 downto 0);
895 
896  full_mode_ctrl_tob_0 : out std_logic_vector(31 downto 0);
897  full_mode_ctrl_bulk_0 : out std_logic_vector(31 downto 0);
898  full_mode_ctrl_bulk_1 : out std_logic_vector(31 downto 0);
899  full_mode_ctrl_bulk_2 : out std_logic_vector(31 downto 0);
900 
901  stage_fifo_level_tob_0 : in std_logic_vector(15 downto 0);
902  stage_fifo_level_bulk_0 : in std_logic_vector(15 downto 0);
903  stage_fifo_level_bulk_1 : in std_logic_vector(15 downto 0);
904  stage_fifo_level_bulk_2 : in std_logic_vector(15 downto 0);
905 
906 
907 
908 
909  stage_fifo_busy_tob_0 : out STD_LOGIC;
910  stage_fifo_busy_bulk_0 : out STD_LOGIC;
911  stage_fifo_busy_bulk_1 : out STD_LOGIC;
912  stage_fifo_busy_bulk_2 : out STD_LOGIC;
913  stage_fifo_xoff_tob_0 : out STD_LOGIC;
914  stage_fifo_xoff_bulk_0 : out STD_LOGIC;
915  stage_fifo_xoff_bulk_1 : out STD_LOGIC;
916  stage_fifo_xoff_bulk_2 : out STD_LOGIC;
917  stage_fifo_full_tob_0 : in STD_LOGIC;
918  stage_fifo_full_bulk_0 : in STD_LOGIC;
919  stage_fifo_full_bulk_1 : in STD_LOGIC;
920  stage_fifo_full_bulk_2 : in STD_LOGIC;
921 
922  flx_backpressure_tob_0 : out STD_LOGIC;
923  flx_backpressure_bulk_0 : out STD_LOGIC;
924  flx_backpressure_bulk_1 : out STD_LOGIC;
925  flx_backpressure_bulk_2 : out STD_LOGIC;
926 
927  pp_clock : in STD_LOGIC;
928  clk_40 : in std_logic;
929  clk_160 : in std_logic;
930  rt_clk : in std_logic;
931  backplane_control : out std_logic_vector(31 downto 0);
932  init_clk : in std_logic;
933  master_reset : in std_logic;
934  rod_slot : in std_logic;
935  cK_pll_lock : in std_logic;
936 
937  CK_INT : in STD_LOGIC;
938  SMBALERT_B : in STD_LOGIC;
939  T_WRN_B : in STD_LOGIC;
940 
941  SYSTEM_RESET : in STD_LOGIC;
942 
943 
944  flx_backpressure : out std_logic_vector(11 downto 0);
945 -- readout_controller ---
946  ro_user_clock : in STD_LOGIC;
947  ro_controller_reset : in STD_LOGIC;
948  ro_txcharisk : out std_logic_vector(3 downto 0);
949  ro_txdata : out std_logic_vector(31 downto 0);
950  ro_status : in std_logic_vector(7 downto 0);
951 
952  aurora_user_clock_0 : in STD_LOGIC;
953  aurora_user_clock_1 : in STD_LOGIC;
954  aurora_user_clock_2 : in STD_LOGIC;
955  aurora_user_clock_3 : in STD_LOGIC;
956  aurora_user_clock_4 : in STD_LOGIC;
957  aurora_user_clock_5 : in STD_LOGIC;
958  aurora_user_clock_6 : in STD_LOGIC;
959  aurora_user_clock_7 : in STD_LOGIC;
960  aurora_user_clock_8 : in STD_LOGIC;
961  aurora_user_clock_9 : in STD_LOGIC;
962  aurora_user_clock_10 : in STD_LOGIC;
963  aurora_user_clock_11 : in STD_LOGIC;
964 
965  aurora_chan_stat_0 : in STD_LOGIC_VECTOR (31 downto 0);
966  aurora_chan_stat_1 : in STD_LOGIC_VECTOR (31 downto 0);
967  aurora_chan_stat_2 : in STD_LOGIC_VECTOR (31 downto 0);
968  aurora_chan_stat_3 : in STD_LOGIC_VECTOR (31 downto 0);
969  aurora_chan_stat_4 : in STD_LOGIC_VECTOR (31 downto 0);
970  aurora_chan_stat_5 : in STD_LOGIC_VECTOR (31 downto 0);
971  aurora_chan_stat_6 : in STD_LOGIC_VECTOR (31 downto 0);
972  aurora_chan_stat_7 : in STD_LOGIC_VECTOR (31 downto 0);
973  aurora_chan_stat_8 : in STD_LOGIC_VECTOR (31 downto 0);
974  aurora_chan_stat_9 : in STD_LOGIC_VECTOR (31 downto 0);
975  aurora_chan_stat_10 : in STD_LOGIC_VECTOR (31 downto 0);
976  aurora_chan_stat_11 : in STD_LOGIC_VECTOR (31 downto 0);
977 
978  aurora_chan_control_0 : out STD_LOGIC_VECTOR (31 downto 0);
979  aurora_chan_control_1 : out STD_LOGIC_VECTOR (31 downto 0);
980  aurora_chan_control_2 : out STD_LOGIC_VECTOR (31 downto 0);
981  aurora_chan_control_3 : out STD_LOGIC_VECTOR (31 downto 0);
982  aurora_chan_control_4 : out STD_LOGIC_VECTOR (31 downto 0);
983  aurora_chan_control_5 : out STD_LOGIC_VECTOR (31 downto 0);
984  aurora_chan_control_6 : out STD_LOGIC_VECTOR (31 downto 0);
985  aurora_chan_control_7 : out STD_LOGIC_VECTOR (31 downto 0);
986  aurora_chan_control_8 : out STD_LOGIC_VECTOR (31 downto 0);
987  aurora_chan_control_9 : out STD_LOGIC_VECTOR (31 downto 0);
988  aurora_chan_control_10 : out STD_LOGIC_VECTOR (31 downto 0);
989  aurora_chan_control_11 : out STD_LOGIC_VECTOR (31 downto 0);
990 
991 
992 
993 
994 
995  bp_data_0 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
996  bp_data_1 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
997  bp_data_2 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
998  bp_data_3 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
999  bp_data_4 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1000  bp_data_5 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1001  bp_data_6 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1002  bp_data_7 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1003  bp_data_8 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1004  bp_data_9 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1005  bp_data_10 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1006  bp_data_11 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1007 
1008  s_axis_tvalid_0 : in std_logic;
1009  s_axis_tvalid_1 : in std_logic;
1010  s_axis_tvalid_2 : in std_logic;
1011  s_axis_tvalid_3 : in std_logic;
1012  s_axis_tvalid_4 : in std_logic;
1013  s_axis_tvalid_5 : in std_logic;
1014  s_axis_tvalid_6 : in std_logic;
1015  s_axis_tvalid_7 : in std_logic;
1016  s_axis_tvalid_8 : in std_logic;
1017  s_axis_tvalid_9 : in std_logic;
1018  s_axis_tvalid_10 : in std_logic;
1019  s_axis_tvalid_11 : in std_logic;
1020 
1021  s_axis_tlast_0 : in std_logic;
1022  s_axis_tlast_1 : in std_logic;
1023  s_axis_tlast_2 : in std_logic;
1024  s_axis_tlast_3 : in std_logic;
1025  s_axis_tlast_4 : in std_logic;
1026  s_axis_tlast_5 : in std_logic;
1027  s_axis_tlast_6 : in std_logic;
1028  s_axis_tlast_7 : in std_logic;
1029  s_axis_tlast_8 : in std_logic;
1030  s_axis_tlast_9 : in std_logic;
1031  s_axis_tlast_10 : in std_logic;
1032  s_axis_tlast_11 : in std_logic;
1033 
1034  s_axis_tready_0 : out std_logic;
1035  s_axis_tready_1 : out std_logic;
1036  s_axis_tready_2 : out std_logic;
1037  s_axis_tready_3 : out std_logic;
1038  s_axis_tready_4 : out std_logic;
1039  s_axis_tready_5 : out std_logic;
1040  s_axis_tready_6 : out std_logic;
1041  s_axis_tready_7 : out std_logic;
1042  s_axis_tready_8 : out std_logic;
1043  s_axis_tready_9 : out std_logic;
1044  s_axis_tready_10 : out std_logic;
1045  s_axis_tready_11 : out std_logic;
1046 
1047  s_axi_ufc_rx_tdata_0 : in std_logic_vector(63 downto 0);
1048  s_axi_ufc_rx_tdata_1 : in std_logic_vector(63 downto 0);
1049  s_axi_ufc_rx_tdata_2 : in std_logic_vector(63 downto 0);
1050  s_axi_ufc_rx_tdata_3 : in std_logic_vector(63 downto 0);
1051  s_axi_ufc_rx_tdata_4 : in std_logic_vector(63 downto 0);
1052  s_axi_ufc_rx_tdata_5 : in std_logic_vector(63 downto 0);
1053  s_axi_ufc_rx_tdata_6 : in std_logic_vector(63 downto 0);
1054  s_axi_ufc_rx_tdata_7 : in std_logic_vector(63 downto 0);
1055  s_axi_ufc_rx_tdata_8 : in std_logic_vector(63 downto 0);
1056  s_axi_ufc_rx_tdata_9 : in std_logic_vector(63 downto 0);
1057  s_axi_ufc_rx_tdata_10 : in std_logic_vector(63 downto 0);
1058  s_axi_ufc_rx_tdata_11 : in std_logic_vector(63 downto 0);
1059 
1060 
1061  s_axi_ufc_rx_tvalid_0 : in std_logic;
1062  s_axi_ufc_rx_tvalid_1 : in std_logic;
1063  s_axi_ufc_rx_tvalid_2 : in std_logic;
1064  s_axi_ufc_rx_tvalid_3 : in std_logic;
1065  s_axi_ufc_rx_tvalid_4 : in std_logic;
1066  s_axi_ufc_rx_tvalid_5 : in std_logic;
1067  s_axi_ufc_rx_tvalid_6 : in std_logic;
1068  s_axi_ufc_rx_tvalid_7 : in std_logic;
1069  s_axi_ufc_rx_tvalid_8 : in std_logic;
1070  s_axi_ufc_rx_tvalid_9 : in std_logic;
1071  s_axi_ufc_rx_tvalid_10 : in std_logic;
1072  s_axi_ufc_rx_tvalid_11 : in std_logic;
1073 
1074 
1075  s_axi_ufc_rx_tlast_0 : in std_logic;
1076  s_axi_ufc_rx_tlast_1 : in std_logic;
1077  s_axi_ufc_rx_tlast_2 : in std_logic;
1078  s_axi_ufc_rx_tlast_3 : in std_logic;
1079  s_axi_ufc_rx_tlast_4 : in std_logic;
1080  s_axi_ufc_rx_tlast_5 : in std_logic;
1081  s_axi_ufc_rx_tlast_6 : in std_logic;
1082  s_axi_ufc_rx_tlast_7 : in std_logic;
1083  s_axi_ufc_rx_tlast_8 : in std_logic;
1084  s_axi_ufc_rx_tlast_9 : in std_logic;
1085  s_axi_ufc_rx_tlast_10 : in std_logic;
1086  s_axi_ufc_rx_tlast_11 : in std_logic;
1087 
1088 
1089 
1090  multichannel_busy : out std_logic;
1091  combined_busy : in std_logic;
1092 
1093  channel_enable_vio : in std_logic_vector (23 downto 0);
1094  first_chan_vio : in std_logic_vector (4 downto 0);
1095  last_chan_vio : in std_logic_vector (4 downto 0);
1096  TTC_ignore_vio : in std_logic;
1097  debug_ctrl_vio : in std_logic;
1098 
1099 --- output queue(s)
1100 
1101  m_tvalid_0 : out STD_LOGIC;
1102  m_tlast_0 : out STD_LOGIC;
1103  m_tdata_0 : out STD_LOGIC_VECTOR ((bp_width-1) downto 0);
1104  m_header_marker_0 : out STD_LOGIC;
1105  m_tail_marker_0 : out STD_LOGIC;
1106  m_tready_0 : in STD_LOGIC;
1107 
1108  bulk_m_tvalid_0 : out STD_LOGIC;
1109  bulk_m_tlast_0 : out STD_LOGIC;
1110  bulk_m_tdata_0 : out STD_LOGIC_VECTOR (63 downto 0);
1111  bulk_m_header_marker_0 : out STD_LOGIC;
1112  bulk_m_tail_marker_0 : out STD_LOGIC;
1113  bulk_m_tready_0 : in STD_LOGIC;
1114 
1115 
1116  bulk_m_tvalid_1 : out STD_LOGIC;
1117  bulk_m_tlast_1 : out STD_LOGIC;
1118  bulk_m_tdata_1 : out STD_LOGIC_VECTOR (63 downto 0);
1119  bulk_m_header_marker_1 : out STD_LOGIC;
1120  bulk_m_tail_marker_1 : out STD_LOGIC;
1121  bulk_m_tready_1 : in STD_LOGIC;
1122 
1123  bulk_m_tvalid_2 : out STD_LOGIC;
1124  bulk_m_tlast_2 : out STD_LOGIC;
1125  bulk_m_tdata_2 : out STD_LOGIC_VECTOR (63 downto 0);
1126  bulk_m_header_marker_2 : out STD_LOGIC;
1127  bulk_m_tail_marker_2 : out STD_LOGIC;
1128  bulk_m_tready_2 : in STD_LOGIC;
1129 
1130 
1131 
1132 
1133 
1134 --TTC signals
1135  cttc_user_clk : in std_logic;
1136  ttc_status : in std_logic_vector(31 downto 0);
1137  ttc_reset : out std_logic;
1138 -- ttc_reset : in std_logic;
1139  ttc_seq : in std_logic_vector(1 downto 0);
1140  ttc_word_0 : in std_logic_vector(31 downto 0);
1141  ttc_word_1 : in std_logic_vector(31 downto 0);
1142  ttc_word_2 : in std_logic_vector(31 downto 0);
1143  ttc_word_3 : in std_logic_vector(31 downto 0);
1144 
1145 
1146  ttc_mux_ctrl : in std_logic;
1147  BP_CTTC_rxdata : in std_logic_vector (31 downto 0);
1148  FM_CTTC_rxdata : in std_logic_vector (31 downto 0);
1149  BP_CTTC_rxcharisk : in std_logic_vector (3 downto 0);
1150  FM_CTTC_rxcharisk : in std_logic_vector (3 downto 0);
1151  BP_CTTC_MGT_bus : in STD_LOGIC_VECTOR(31 DOWNTO 0);
1152  FM_CTTC_MGT_bus : in STD_LOGIC_VECTOR(31 DOWNTO 0);
1153  BP_CTTC_rxoutclk : in STD_LOGIC;
1154  FM_CTTC_rxoutclk : in STD_LOGIC
1155 
1156 
1157 
1158 
1159  );
1160 
1161 
1162  end component;
1163 
1164  component system_top_reset
1165  generic (
1166  max_count : std_logic_vector := x"0FFFFFFF"
1167  );
1168  port (
1169  clk40 : in STD_LOGIC;
1170  rod_button : in STD_LOGIC;
1171  sys_top_reset : out STD_LOGIC;
1172  sys_top_reset_b : out STD_LOGIC
1173 
1174  );
1175  end component;
1176 
1177  component reset_count is
1178  generic
1179  (
1180  COUNTER_WIDTH : integer := 5
1181  );
1182 
1183  Port (
1184  clock : in STD_LOGIC;
1185  power_down_b: out STD_LOGIC
1186  );
1187  end component;
1188 
1189 
1190 
1191 
1192 
1193  component IBUF
1194  port (
1195  O : out std_ulogic;
1196  I : in std_ulogic);
1197 
1198  end component;
1199 
1200 
1201 
1202 COMPONENT pp_ctrl_vio
1203  PORT (
1204  clk : IN STD_LOGIC;
1205  probe_out0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
1206  probe_out1 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
1207  probe_out2 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
1208  probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1209  probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1210  probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1211  );
1212 END COMPONENT;
1213 
1214 
1215 
1216 
1217 
1218 component FM_ROD is
1219  generic(
1220  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1221  NUM_LINKS : integer := 4;
1222  RECOVER_CLK_FROM_RX_GBT : boolean := false);
1223  port (
1224 -- GTREFCLK0_N_IN : in std_logic;
1225 -- GTREFCLK0_P_IN : in std_logic;
1226  GTREFCLK0 : in std_logic;
1227  RESET_BUTTON : in std_logic;
1228 
1229 
1230  app_clk_in : in std_logic;
1231  gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1232  gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1233  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1234  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1235 
1236  s_axis_tvalid : in std_logic;
1237  s_axis_tlast : in std_logic;
1238  s_axis_tready : out std_logic;
1239  s_axis_tdata : in std_logic_vector(31 downto 0);
1240  TXOUTCLK_0 : out std_logic;
1241  channel_reset : in std_logic;
1242  TestMode : in std_logic;
1243  interface_reset : out std_logic
1244 
1245 
1246  );
1247  end component;
1248 
1249 component Full_Mode_Tx is
1250 
1251  generic(
1252  DEBUG : integer := 0;
1253  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1254  NUM_LINKS : integer := 2;
1255  RECOVER_CLK_FROM_RX_GBT : boolean := false);
1256 port (
1257 -- GTREFCLK0_N_IN : in std_logic;
1258 -- GTREFCLK0_P_IN : in std_logic;
1259  GTREFCLK0 : in std_logic;
1260  pp_clock : in std_logic;
1261  RESET_BUTTON : in std_logic;
1262 
1263 
1264  app_clk_in : in std_logic;
1265  gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1266  gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1267  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1268  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1269 
1270 
1271 
1272  s_axis_tvalid_0 : in std_logic;
1273  s_axis_tlast_0 : in std_logic;
1274  s_axis_tready_0 : out std_logic;
1275  flx_bp_240_0 : in std_logic; --felix back pressure
1276  s_axis_tdata_0 : in std_logic_vector(31 downto 0);
1277  TXOUTCLK_0 : out std_logic;
1278  channel_reset_0 : in std_logic;
1279  soft_reset_0 : in std_logic;
1280  busy_0 : in std_logic;
1281  -- TestMode_0 : in std_logic;
1282  interface_reset_0 : out std_logic;
1283 
1284  s_axis_tvalid_1 : in std_logic;
1285  s_axis_tlast_1 : in std_logic;
1286  s_axis_tready_1 : out std_logic;
1287  flx_bp_240_1 : in std_logic; --felix back pressure
1288  s_axis_tdata_1 : in std_logic_vector(31 downto 0);
1289 -- TXOUTCLK_1 : out std_logic;
1290  channel_reset_1 : in std_logic;
1291  soft_reset_1 : in std_logic;
1292  busy_1 : in std_logic;
1293 -- TestMode_1 : in std_logic;
1294  interface_reset_1 : out std_logic;
1295 
1296  full_mode_ctrl_0 : in STD_LOGIC_VECTOR (31 downto 0);
1297  full_mode_ctrl_1 : in STD_LOGIC_VECTOR (31 downto 0);
1298  full_mode_stat_0 : out STD_LOGIC_VECTOR (31 downto 0);
1299  full_mode_stat_1 : out STD_LOGIC_VECTOR (31 downto 0);
1300  FM_L1id_stat_0 : out std_logic_vector(31 downto 0);
1301  FM_L1id_stat_1 : out std_logic_vector(31 downto 0)
1302 
1303 
1304 
1305  );
1306 
1307 end component;
1308 
1309 component Full_Mode_CTTC
1310  generic(
1311  DEBUG : integer := 0;
1312 -- SIM : integer := 0;
1313  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1314  NUM_LINKS : integer := 2;
1315  RECOVER_CLK_FROM_RX_GBT : boolean := false;
1316  EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;
1317  EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch
1318  EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM
1319  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
1320  STABLE_CLOCK_PERIOD : integer := 24;
1321  EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive re
1322  );
1323 
1324 
1325 port (
1326 -- GTREFCLK0_N_IN : in std_logic;
1327 -- GTREFCLK0_P_IN : in std_logic;
1328  GTREFCLK0 : in std_logic;
1329  pp_clock : in std_logic;
1330  RESET_BUTTON : in std_logic;
1331 
1332  app_clk_in : in std_logic;
1333 -- gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1334 -- gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1335  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1336  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1337 
1338  s_axis_tvalid_0 : in std_logic;
1339  s_axis_tlast_0 : in std_logic;
1340  s_axis_tready_0 : out std_logic;
1341  flx_bp_240_0 : in std_logic; --felix back pressure
1342  s_axis_tdata_0 : in std_logic_vector(31 downto 0);
1343  TXOUTCLK_0 : out std_logic;
1344  channel_reset_0 : in std_logic;
1345  soft_reset_0 : in std_logic;
1346  busy_0 : in std_logic;
1347  --replaced by fm_control
1348  --TestMode_0 : in std_logic;
1349  interface_reset_0 : out std_logic;
1350 
1351  s_axis_tvalid_1 : in std_logic;
1352  s_axis_tlast_1 : in std_logic;
1353  s_axis_tready_1 : out std_logic;
1354  flx_bp_240_1 : in std_logic; --felix back pressure
1355  s_axis_tdata_1 : in std_logic_vector(31 downto 0);
1356 -- TXOUTCLK_1 : out std_logic;
1357  channel_reset_1 : in std_logic;
1358  soft_reset_1 : in std_logic;
1359  busy_1 : in std_logic;
1360 -- TestMode_1 : in std_logic;
1361  interface_reset_1 : out std_logic;
1362  full_mode_ctrl_0 : in STD_LOGIC_VECTOR (31 downto 0);
1363  full_mode_ctrl_1 : in STD_LOGIC_VECTOR (31 downto 0);
1364  --full_mode_ctrl(0) = soft reset (must be toggled high then low)
1365  --full_mode_ctrl(1) = enable playout
1366  --full_mode_ctrl(2) = assert FM busy out
1367  --full_mode_ctrl(2) = assert LEMO
1368 
1369  full_mode_stat_0 : out STD_LOGIC_VECTOR (31 downto 0);
1370  full_mode_stat_1 : out STD_LOGIC_VECTOR (31 downto 0);
1371  --full_mode_stat(0) = 270 MHz MMCM locked
1372  --full_mode_stat(1) = reset done
1373  --full_mode_stat(1) = Start of Packet (SOP)
1374  --full_mode_stat(1) = End of Packet (EOP)
1375  --full_mode_stat(26 downto 16) = fifo fill level = fifo34_count
1376  FM_L1id_stat_0 : out std_logic_vector(31 downto 0);
1377  FM_L1id_stat_1 : out std_logic_vector(31 downto 0);
1378 
1379  --***** CTTC PORTS ***********************************
1380  gt_refclk_q219_c0 : in std_logic;
1381 -- Q9_CLK0_GTREFCLK_IN_P : in std_logic;
1382 -- Q9_CLK0_GTREFCLK_IN_N : in std_logic;
1383  DRP_CLK_IN : in std_logic;
1384  gt0_rxusrclk : out std_logic;
1385  TRACK_DATA_OUT : out std_logic;
1386  ttc_word_0 : out std_logic_vector(31 downto 0);
1387  ttc_word_1 : out std_logic_vector(31 downto 0);
1388  ttc_word_2 : out std_logic_vector(31 downto 0);
1389  ttc_word_3 : out std_logic_vector(31 downto 0);
1390  ttc_seq : out std_logic_vector(1 downto 0);
1391  ttc_status : out std_logic_vector(31 downto 0);
1392  ttc_reset : in std_logic;
1393  stop_ttc_info : in STD_LOGIC;
1394 
1395  cttc_cpllreset_in : in STD_LOGIC;
1396  gt0_cpllpd_in : in std_logic;
1397  gt0_rxbufreset_in : in STD_LOGIC;
1398  gt0_rxpcsreset_in : in STD_LOGIC;
1399  gt0_rxpmareset_in : in STD_LOGIC;
1400  gt0_rxcdrhold_in : in STD_LOGIC;
1401  gt0_rxpd_in : in STD_LOGIC;
1402 
1403  CTTC_RXN_IN : in std_logic;
1404  CTTC_RXP_IN : in std_logic;
1405 
1406  FM_CTTC_rxdata : out std_logic_vector (31 downto 0);
1407  FM_CTTC_rxcharisk : out std_logic_vector (3 downto 0);
1408  FM_CTTC_MGT_bus : out STD_LOGIC_VECTOR(31 DOWNTO 0);
1409  FM_CTTC_rxoutclk : out std_logic
1410  );
1411 
1412 end component;
1413 
1414 
1415 
1416 
1417 
1418 
1419 component packet_fifo
1420  Port (
1421  --Slave (input) side
1422  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
1423  s_axis_tvalid : IN STD_LOGIC;
1424  s_axis_tlast : IN STD_LOGIC;
1425  s_axis_tready : OUT STD_LOGIC;
1426 
1427  --Master (output) side
1428  m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1429  m_axis_tvalid : OUT STD_LOGIC;
1430  m_axis_tready : IN STD_LOGIC;
1431  m_axis_tlast : OUT STD_LOGIC;
1432 
1433  --control
1434  -- DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1435  WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1436  RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1437  fifo_full : out STD_LOGIC;
1438  clk_160 : in std_logic;
1439  clk_240 : in std_logic;
1440  RESET : in std_logic;
1441  flx_backpressure : in std_logic;
1442  flx_bp_enable : in std_logic;
1443  flx_bp_240 : out std_logic
1444 
1445  );
1446 end component;
1447 
1448 COMPONENT vio_top
1449  PORT (
1450  clk : IN STD_LOGIC;
1451  probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1452  probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1453  probe_in2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1454  probe_in3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1455  probe_in4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1456  probe_in5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1457  probe_in6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1458  probe_in7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1459  probe_in8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1460  probe_in9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1461  probe_in10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1462  probe_in11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1463  probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1464  probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1465  probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1466  probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1467  probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1468  probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1469  probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1470  );
1471 END COMPONENT;
1472 
1473 COMPONENT vio_ttc
1474  PORT (
1475  clk : IN STD_LOGIC;
1476  probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1477  probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1478  );
1479 END COMPONENT;
1480 
1481  signal ipbr_backplane : ipb_rbus;
1482  signal ipbw_backplane : ipb_wbus;
1483  signal ipbr_Processor : ipb_rbus;
1484  signal ipbw_Processor : ipb_wbus;
1485  signal ipb_clk : std_logic;
1486  signal ipb_rst : std_logic;
1487 -- signal ipbr_backplane : ipb_rbus_array(0 downto 0);
1488 -- signal ipbw_backplane : ipb_wbus_array(0 downto 0);
1489 
1490  signal geo_location : STD_LOGIC_VECTOR (7 downto 0);
1491  signal flx_bp_bus : STD_LOGIC_VECTOR (11 downto 0);
1492 
1493  signal pp_clock : std_logic;
1494  signal rt_clk : std_logic;
1495  signal clk_160 : std_logic;
1496  signal backplane_control : std_logic_vector(31 downto 0);
1497 
1498  signal cttc_cpllreset_in : std_logic;
1499  signal cttc_cpllpd_in : STD_LOGIC;
1500  signal cttc_rxbufreset_in : STD_LOGIC;
1501  signal cttc_rxpcsreset_in : STD_LOGIC;
1502  signal cttc_rxpmareset_in : STD_LOGIC;
1503  signal cttc_rxcdrhold_in : STD_LOGIC;
1504  signal cttc_rxpd_in : STD_LOGIC;
1505 
1506 -- AXI4 lite bus from IPbus to packet processor
1507  signal pkt_areset : std_logic;
1508  signal packet_proc_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
1509  signal packet_proc_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
1510  signal packet_proc_arready : STD_LOGIC;
1511  signal packet_proc_arvalid : STD_LOGIC;
1512  signal packet_proc_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
1513  signal packet_proc_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
1514  signal packet_proc_awready : STD_LOGIC;
1515  signal packet_proc_awvalid : STD_LOGIC;
1516  signal packet_proc_bready : STD_LOGIC;
1517  signal packet_proc_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
1518  signal packet_proc_bvalid : STD_LOGIC;
1519  signal packet_proc_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
1520  signal packet_proc_rready : STD_LOGIC;
1521  signal packet_proc_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
1522  signal packet_proc_rvalid : STD_LOGIC;
1523  signal packet_proc_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
1524  signal packet_proc_wready : STD_LOGIC;
1525  signal packet_proc_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
1526  signal packet_proc_wvalid : STD_LOGIC;
1527  signal pkt_ARESETN : STD_LOGIC;
1528  signal PKT_CLK : STD_LOGIC;
1529  signal CLK_40 : STD_LOGIC;
1530  signal CLK_40_pin : STD_LOGIC;
1531  signal CLK_125 : STD_LOGIC;
1532  signal gp_button_i : STD_LOGIC;
1533  signal GTCLK_q218 : STD_LOGIC;
1534 
1535  signal multichannel_busy : std_logic;
1536  signal combined_busy : std_logic;
1537  signal lemo_i : std_logic;
1538 
1539  signal bulk_m_tvalid_0 : STD_LOGIC;
1540  signal bulk_m_tlast_0 : STD_LOGIC;
1541  signal bulk_m_tdata_0 : STD_LOGIC_VECTOR (63 downto 0);
1542  signal bulk_m_header_marker_0 : STD_LOGIC;
1543  signal bulk_m_tail_marker_0 : STD_LOGIC;
1544  signal bulk_m_tready_0 : STD_LOGIC;
1545 
1546  signal bulk_fm_tvalid_0 : STD_LOGIC;
1547  signal bulk_fm_tlast_0 : STD_LOGIC;
1548  signal bulk_fm_tdata_0 : STD_LOGIC_VECTOR (31 downto 0);
1549  signal bulk_fm_tready_0 : STD_LOGIC;
1550  signal flx_bp_240_bulk_0 : std_logic;
1551 
1552  signal bulk_m_tvalid_1 : STD_LOGIC;
1553  signal bulk_m_tlast_1 : STD_LOGIC;
1554  signal bulk_m_tdata_1 : STD_LOGIC_VECTOR (63 downto 0);
1555  signal bulk_m_header_marker_1 : STD_LOGIC;
1556  signal bulk_m_tail_marker_1 : STD_LOGIC;
1557  signal bulk_m_tready_1 : STD_LOGIC;
1558 
1559  signal bulk_fm_tvalid_1 : STD_LOGIC;
1560  signal bulk_fm_tlast_1 : STD_LOGIC;
1561  signal bulk_fm_tdata_1 : STD_LOGIC_VECTOR (31 downto 0);
1562  signal bulk_fm_tready_1 : STD_LOGIC;
1563  signal flx_bp_240_bulk_1 : std_logic;
1564 
1565 
1566 
1567  signal bulk_m_tvalid_2 : STD_LOGIC;
1568  signal bulk_m_tlast_2 : STD_LOGIC;
1569  signal bulk_m_tdata_2 : STD_LOGIC_VECTOR (63 downto 0);
1570  signal bulk_m_header_marker_2 : STD_LOGIC;
1571  signal bulk_m_tail_marker_2 : STD_LOGIC;
1572  signal bulk_m_tready_2 : STD_LOGIC;
1573 
1574  signal bulk_fm_tvalid_2 : STD_LOGIC;
1575  signal bulk_fm_tlast_2 : STD_LOGIC;
1576  signal bulk_fm_tdata_2 : STD_LOGIC_VECTOR (31 downto 0);
1577  signal bulk_fm_tready_2 : STD_LOGIC;
1578  signal flx_bp_240_bulk_2 : std_logic;
1579 
1580  signal FM1_reset_0 : STD_LOGIC;
1581  signal FM1_reset_1 : STD_LOGIC;
1582  signal FM2_reset_0 : STD_LOGIC;
1583  signal FM2_reset_1 : STD_LOGIC;
1584 
1585  signal fm_soft_reset : STD_LOGIC;
1586 
1587  signal stage_fifo_level_tob_0 : STD_LOGIC_VECTOR (31 downto 0);
1588  signal stage_fifo_level_bulk_0 : STD_LOGIC_VECTOR (31 downto 0);
1589  signal stage_fifo_level_bulk_1 : STD_LOGIC_VECTOR (31 downto 0);
1590  signal stage_fifo_level_bulk_2 : STD_LOGIC_VECTOR (31 downto 0);
1591 
1592 
1593  signal stage_fifo_full_tob_0 : std_logic;
1594  signal stage_fifo_full_bulk_0 : std_logic;
1595  signal stage_fifo_full_bulk_1 : std_logic;
1596  signal stage_fifo_full_bulk_2 : std_logic;
1597 
1598  signal stage_fifo_busy_tob_0 : std_logic;
1599  signal stage_fifo_busy_bulk_0 : std_logic;
1600  signal stage_fifo_busy_bulk_1 : std_logic;
1601  signal stage_fifo_busy_bulk_2 : std_logic;
1602 
1603  signal stage_fifo_xoff_tob_0 : std_logic;
1604  signal stage_fifo_xoff_bulk_0 : std_logic;
1605  signal stage_fifo_xoff_bulk_1 : std_logic;
1606  signal stage_fifo_xoff_bulk_2 : std_logic;
1607 
1608  signal flx_backpressure_tob_0 : STD_LOGIC;
1609  signal flx_backpressure_bulk_0 : STD_LOGIC;
1610  signal flx_backpressure_bulk_1 : STD_LOGIC;
1611  signal flx_backpressure_bulk_2 : STD_LOGIC;
1612 -- AXI4 Streaming bus signals from Aurora Interface to Packet Processor
1613 
1614 
1615  signal CHANNEL_STAT_3 : STD_LOGIC_VECTOR (31 downto 0);
1616  signal CHANNEL_CTRL_3 : STD_LOGIC_VECTOR (31 downto 0);
1617  signal m_axi_rx_tdata_3 : std_logic_vector (63 downto 0);
1618  signal m_axi_rx_tvalid_3 : STD_LOGIC;
1619  signal m_axi_rx_tlast_3 : STD_LOGIC;
1620  -- signal m_axi_rx_tkeep_3 : std_logic_vector (7 downto 0);
1621 
1622  signal m_axi_ufc_rx_tdata_3 : STD_LOGIC_vector (63 downto 0);
1623  signal m_axi_ufc_rx_tvalid_3 : STD_LOGIC;
1624  signal m_axi_ufc_rx_tlast_3 : STD_LOGIC;
1625  signal user_clk_out_3 : STD_LOGIC;
1626 
1627  signal CHANNEL_STAT_4 : STD_LOGIC_VECTOR (31 downto 0);
1628  signal CHANNEL_CTRL_4 : STD_LOGIC_VECTOR (31 downto 0);
1629  signal m_axi_rx_tdata_4 : std_logic_vector (63 downto 0);
1630  signal m_axi_rx_tvalid_4 : STD_LOGIC;
1631  signal m_axi_rx_tlast_4 : STD_LOGIC;
1632  signal m_axi_rx_tkeep_4 : std_logic_vector (7 downto 0);
1633  signal m_axi_ufc_rx_tdata_4 : STD_LOGIC_vector (63 downto 0);
1634  signal m_axi_ufc_rx_tvalid_4 : STD_LOGIC;
1635  signal m_axi_ufc_rx_tlast_4 : STD_LOGIC;
1636  signal user_clk_out_4 : STD_LOGIC;
1637 
1638 
1639  signal CHANNEL_STAT_5 : STD_LOGIC_VECTOR (31 downto 0);
1640  signal CHANNEL_CTRL_5 : STD_LOGIC_VECTOR (31 downto 0);
1641  signal m_axi_rx_tdata_5 : std_logic_vector (63 downto 0);
1642  signal m_axi_rx_tvalid_5 : STD_LOGIC;
1643  signal m_axi_rx_tlast_5 : STD_LOGIC;
1644  signal m_axi_rx_tkeep_5 : std_logic_vector (7 downto 0);
1645  signal m_axi_ufc_rx_tdata_5 : STD_LOGIC_vector (63 downto 0);
1646  signal m_axi_ufc_rx_tvalid_5 : STD_LOGIC;
1647  signal m_axi_ufc_rx_tlast_5 : STD_LOGIC;
1648  signal user_clk_out_5 : STD_LOGIC;
1649 
1650  signal CHANNEL_STAT_6 : STD_LOGIC_VECTOR (31 downto 0);
1651  signal CHANNEL_CTRL_6 : STD_LOGIC_VECTOR (31 downto 0);
1652  signal m_axi_rx_tdata_6 : std_logic_vector (63 downto 0);
1653  signal m_axi_rx_tvalid_6 : STD_LOGIC;
1654  signal m_axi_rx_tlast_6 : STD_LOGIC;
1655  signal m_axi_ufc_rx_tdata_6 : STD_LOGIC_vector (63 downto 0);
1656  signal m_axi_ufc_rx_tvalid_6 : STD_LOGIC;
1657  signal m_axi_ufc_rx_tlast_6 : STD_LOGIC;
1658  signal user_clk_out_6 : STD_LOGIC;
1659 
1660  signal CHANNEL_STAT_7 : STD_LOGIC_VECTOR (31 downto 0);
1661  signal CHANNEL_CTRL_7 : STD_LOGIC_VECTOR (31 downto 0);
1662  signal m_axi_rx_tdata_7 : std_logic_vector (63 downto 0);
1663  signal m_axi_rx_tvalid_7 : STD_LOGIC;
1664  signal m_axi_rx_tlast_7 : STD_LOGIC;
1665  signal m_axi_ufc_rx_tdata_7 : STD_LOGIC_vector (63 downto 0);
1666  signal m_axi_ufc_rx_tvalid_7 : STD_LOGIC;
1667  signal m_axi_ufc_rx_tlast_7 : STD_LOGIC;
1668  signal user_clk_out_7 : STD_LOGIC;
1669 
1670  signal CHANNEL_STAT_8 : STD_LOGIC_VECTOR (31 downto 0);
1671  signal CHANNEL_CTRL_8 : STD_LOGIC_VECTOR (31 downto 0);
1672  signal m_axi_rx_tdata_8 : std_logic_vector (63 downto 0);
1673  signal m_axi_rx_tvalid_8 : STD_LOGIC;
1674  signal m_axi_rx_tlast_8 : STD_LOGIC;
1675  signal m_axi_ufc_rx_tdata_8 : STD_LOGIC_vector (63 downto 0);
1676  signal m_axi_ufc_rx_tvalid_8 : STD_LOGIC;
1677  signal m_axi_ufc_rx_tlast_8 : STD_LOGIC;
1678  signal user_clk_out_8 : STD_LOGIC;
1679 
1680  signal CHANNEL_STAT_9 : STD_LOGIC_VECTOR (31 downto 0);
1681  signal CHANNEL_CTRL_9 : STD_LOGIC_VECTOR (31 downto 0);
1682  signal m_axi_rx_tdata_9 : std_logic_vector (63 downto 0);
1683  signal m_axi_rx_tvalid_9 : STD_LOGIC;
1684  signal m_axi_rx_tlast_9 : STD_LOGIC;
1685  signal m_axi_ufc_rx_tdata_9 : STD_LOGIC_vector (63 downto 0);
1686  signal m_axi_ufc_rx_tvalid_9 : STD_LOGIC;
1687  signal m_axi_ufc_rx_tlast_9 : STD_LOGIC;
1688  signal user_clk_out_9 : STD_LOGIC;
1689 
1690  signal CHANNEL_STAT_10 : STD_LOGIC_VECTOR (31 downto 0);
1691  signal CHANNEL_CTRL_10 : STD_LOGIC_VECTOR (31 downto 0);
1692  signal m_axi_rx_tdata_10 : std_logic_vector (63 downto 0);
1693  signal m_axi_rx_tvalid_10 : STD_LOGIC;
1694  signal m_axi_rx_tlast_10 : STD_LOGIC;
1695  signal m_axi_ufc_rx_tdata_10 : STD_LOGIC_vector (63 downto 0);
1696  signal m_axi_ufc_rx_tvalid_10 : STD_LOGIC;
1697  signal m_axi_ufc_rx_tlast_10 : STD_LOGIC;
1698  signal user_clk_out_10 : STD_LOGIC;
1699 
1700  signal CHANNEL_STAT_11 : STD_LOGIC_VECTOR (31 downto 0);
1701  signal CHANNEL_CTRL_11 : STD_LOGIC_VECTOR (31 downto 0);
1702  signal m_axi_rx_tdata_11 : std_logic_vector (63 downto 0);
1703  signal m_axi_rx_tvalid_11 : STD_LOGIC;
1704  signal m_axi_rx_tlast_11 : STD_LOGIC;
1705  signal m_axi_ufc_rx_tdata_11 : STD_LOGIC_vector (63 downto 0);
1706  signal m_axi_ufc_rx_tvalid_11 : STD_LOGIC;
1707  signal m_axi_ufc_rx_tlast_11 : STD_LOGIC;
1708  signal user_clk_out_11 : STD_LOGIC;
1709 
1710  signal CHANNEL_STAT_12 : STD_LOGIC_VECTOR (31 downto 0);
1711  signal CHANNEL_CTRL_12 : STD_LOGIC_VECTOR (31 downto 0);
1712  signal m_axi_rx_tdata_12 : std_logic_vector (63 downto 0);
1713  signal m_axi_rx_tvalid_12 : STD_LOGIC;
1714  signal m_axi_rx_tlast_12 : STD_LOGIC;
1715  signal m_axi_ufc_rx_tdata_12 : STD_LOGIC_vector (63 downto 0);
1716  signal m_axi_ufc_rx_tvalid_12 : STD_LOGIC;
1717  signal m_axi_ufc_rx_tlast_12 : STD_LOGIC;
1718  signal user_clk_out_12 : STD_LOGIC;
1719 
1720  signal CHANNEL_STAT_13 : STD_LOGIC_VECTOR (31 downto 0);
1721  signal CHANNEL_CTRL_13 : STD_LOGIC_VECTOR (31 downto 0);
1722  signal m_axi_rx_tdata_13 : std_logic_vector (63 downto 0);
1723  signal m_axi_rx_tvalid_13 : STD_LOGIC;
1724  signal m_axi_rx_tlast_13 : STD_LOGIC;
1725  signal m_axi_ufc_rx_tdata_13 : STD_LOGIC_vector (63 downto 0);
1726  signal m_axi_ufc_rx_tvalid_13 : STD_LOGIC;
1727  signal m_axi_ufc_rx_tlast_13 : STD_LOGIC;
1728  signal user_clk_out_13 : STD_LOGIC;
1729 
1730  signal CHANNEL_STAT_14 : STD_LOGIC_VECTOR (31 downto 0);
1731  signal CHANNEL_CTRL_14 : STD_LOGIC_VECTOR (31 downto 0);
1732  signal m_axi_rx_tdata_14 : std_logic_vector (63 downto 0);
1733  signal m_axi_rx_tvalid_14 : STD_LOGIC;
1734  signal m_axi_rx_tlast_14 : STD_LOGIC;
1735  signal m_axi_ufc_rx_tdata_14 : STD_LOGIC_vector (63 downto 0);
1736  signal m_axi_ufc_rx_tvalid_14 : STD_LOGIC;
1737  signal m_axi_ufc_rx_tlast_14 : STD_LOGIC;
1738  signal user_clk_out_14 : STD_LOGIC;
1739 
1740  signal channel_enable_vio : std_logic_vector (23 downto 0);
1741  signal first_chan_vio : std_logic_vector (4 downto 0);
1742  signal last_chan_vio : std_logic_vector (4 downto 0);
1743  signal TTC_ignore_vio : std_logic;
1744  signal debug_ctrl_vio : std_logic;
1745 
1746  signal pp0_m_axi_tdata : std_logic_vector (63 downto 0);
1747  signal pp0_m_axi_tvalid : STD_LOGIC;
1748  signal pp0_m_axi_tlast : STD_LOGIC;
1749  signal pp0_m_axi_tready : STD_LOGIC;
1750 
1751  signal pp_soft_reset_vio : STD_LOGIC;
1752  signal pp_reset : STD_LOGIC;
1753 
1754 
1755 
1756  signal fifo_AXI4_TDATA : std_logic_vector (31 downto 0);
1757  signal fifo_AXI4_TVALID : STD_LOGIC;
1758  signal felix_bulk_TREADY_0 : STD_LOGIC;
1759  signal fifo_AXI4_tlast : STD_LOGIC;
1760 
1761 
1762  signal ppout_fifo_AXI4_TDATA : std_logic_vector (31 downto 0);
1763  signal ppout_fifo_AXI4_TVALID : STD_LOGIC;
1764  signal felix_ch1_AXI4_TREADY : STD_LOGIC;
1765  signal ppout_fifo_AXI4_tlast : STD_LOGIC;
1766  signal flx_bp_240_tob_0 : STD_LOGIC;
1767 
1768 
1769  signal FM_TXOUTCLK : STD_LOGIC;
1770  signal FM_TXOUTCLK_2 : STD_LOGIC;
1771 -- signal FM_reset_0 : STD_LOGIC;
1772 -- signal FM_reset_1 : STD_LOGIC;
1773  signal GTREFCLK_Q217_C0 : STD_LOGIC;
1774 
1775  signal gp_button_ibuf : STD_LOGIC;
1776  signal vio_reset : STD_LOGIC;
1777  signal sys_top_reset : STD_LOGIC;
1778  signal MASTER_RESET : STD_LOGIC;
1779  signal rx_GTReset : STD_LOGIC;
1780  signal rx_reset : STD_LOGIC;
1781 
1782 --TTC signals
1783 
1784  signal ttc_word_0 : std_logic_vector(31 downto 0);
1785  signal ttc_word_1 : std_logic_vector(31 downto 0);
1786  signal ttc_word_2 : std_logic_vector(31 downto 0);
1787  signal ttc_word_3 : std_logic_vector(31 downto 0);
1788  signal ttc_seq : std_logic_vector(1 downto 0);
1789  signal cttc_usrclk : std_logic;
1790  signal L1A : std_logic;
1791  signal l1id_mis_stretch : std_logic;
1792  signal vio_chan_reset : std_logic;
1793  signal sys_top_reset_b : std_logic;
1794 
1795 
1796 
1797 signal spi_pwr1 : std_logic := '0';
1798 signal spi_pwr2 : std_logic := '0';
1799 
1800  signal ro_user_clock : STD_LOGIC;
1801  signal ro_controller_reset : STD_LOGIC;
1802  signal ro_txcharisk : std_logic_vector(3 downto 0);
1803  signal ro_txdata : std_logic_vector(31 downto 0);
1804  signal ro_status : std_logic_vector(7 downto 0);
1805  signal ttc_status : std_logic_vector(31 downto 0);
1806  signal ttc_reset : std_logic;
1807 
1808  signal full_mode_stat_tob_0 : std_logic_vector(31 downto 0);
1809  signal full_mode_stat_bulk_0 : std_logic_vector(31 downto 0);
1810  signal full_mode_stat_bulk_1 : std_logic_vector(31 downto 0);
1811  signal full_mode_stat_bulk_2 : std_logic_vector(31 downto 0);
1812 
1813  signal FM_L1id_stat_tob_0 : std_logic_vector(31 downto 0);
1814  signal FM_L1id_stat_bulk_0 : std_logic_vector(31 downto 0);
1815  signal FM_L1id_stat_bulk_1 : std_logic_vector(31 downto 0);
1816  signal FM_L1id_stat_bulk_2 : std_logic_vector(31 downto 0);
1817 
1818  signal full_mode_ctrl_tob_0 : std_logic_vector(31 downto 0);
1819  signal full_mode_ctrl_bulk_0 : std_logic_vector(31 downto 0);
1820  signal full_mode_ctrl_bulk_1 : std_logic_vector(31 downto 0);
1821  signal full_mode_ctrl_bulk_2 : std_logic_vector(31 downto 0);
1822 
1823  signal gt_refclk_q219_c0 : std_logic;
1824 
1825  signal FM_CTTC_rxdata : std_logic_vector (31 downto 0);
1826  signal FM_CTTC_rxcharisk : std_logic_vector (3 downto 0);
1827  signal FM_CTTC_MGT_bus : STD_LOGIC_VECTOR(31 DOWNTO 0);
1828  signal FM_CTTC_rxoutclk : std_logic;
1829  signal BP_CTTC_rxdata : std_logic_vector (31 downto 0);
1830  signal BP_CTTC_rxcharisk : std_logic_vector (3 downto 0);
1831  signal BP_CTTC_MGT_bus : STD_LOGIC_VECTOR(31 DOWNTO 0);
1832  signal BP_CTTC_rxoutclk : std_logic;
1833  signal ttc_mux_ctrl : std_logic;
1834 
1835 begin
1836 
1837  reset_top : system_top_reset
1838  generic map (
1839  max_count => x"0000FFFF"
1840  )
1841  port map (
1842  clk40 => CLK_40,
1843  rod_button => gp_button_i,
1844  sys_top_reset => sys_top_reset,
1845 -- sys_top_reset_b => phy_resetn
1846  sys_top_reset_b => sys_top_reset_b
1847  );
1848 
1849 --phy_resetn <= sys_top_reset_b;
1850 t_pod0_rst_b <= sys_top_reset_b;
1851 t_pod1_rst_b <= sys_top_reset_b;
1852 t_pod2_rst_b <= sys_top_reset_b;
1853 r_pod_rst_b <= sys_top_reset_b;
1854 
1855 
1856 phy_reset : system_top_reset
1857  generic map (
1858  max_count => x"02625A00" --1 second
1859  )
1860  port map (
1861  clk40 => CLK_40,
1862  rod_button => gp_button_i,
1863  sys_top_reset => open,
1864  sys_top_reset_b => phy_resetn
1865  );
1866 
1867 
1868 
1869 
1870 
1871 
1872 --temporary tie off until location is enabled in Hub-----
1873 --geo_location <= x"00";
1874 
1875  proc_clock_gen : packet_processor_clock
1876  port map (
1877  -- Clock out ports
1878  pp_clock => pp_clock,
1879  rt_clock => rt_clk,
1880  -- Status and control signals
1881  locked => open,
1882  -- Clock in ports
1883  clk_in1 => CLK_40
1884  );
1885 
1886 
1887 top_vio : vio_top
1888  PORT MAP (
1889  clk => CLK_40,
1890  probe_in0(0) => MASTER_RESET,
1891  probe_in1(0) => sys_top_reset,
1892  probe_in2(0) => backplane_control(30), --gp_button_i,
1893 -- probe_in3(0) => rx_GTReset,
1894  probe_in3(0) => LEMO_i,
1895 -- probe_in4(0) => rx_reset,
1896  probe_in4(0) => rotary_switch(0),
1897  probe_in5(0) => rotary_switch(1),
1898  probe_in6(0) => rotary_switch(2),
1899  probe_in7(0) => rotary_switch(3),
1900  probe_in8(0) => CHANNEL_STAT_3(0),
1901  probe_in9(0) => CHANNEL_STAT_4(0),
1902  probe_in10(0) => CHANNEL_STAT_5(0),
1903  probe_in11(0) =>backplane_control(0),
1904  probe_out0(0) => vio_reset,
1905  probe_out1(0) => cttc_cpllpd_in,
1906  probe_out2(0) => cttc_rxbufreset_in,
1907  probe_out3(0) => cttc_rxpcsreset_in,
1908  probe_out4(0) => cttc_rxpmareset_in,
1909  probe_out5(0) => cttc_rxcdrhold_in,
1910  probe_out6(0) => cttc_rxpd_in
1911  );
1912 
1913 
1914 
1915  ipbus_blk : rod_system
1916  generic map (
1917  GLOBAL_DATE => GLOBAL_DATE,
1918  GLOBAL_TIME => GLOBAL_TIME,
1919  GLOBAL_VER => GLOBAL_VER,
1920  GLOBAL_SHA => GLOBAL_SHA,
1921  TOP_VER => TOP_VER,
1922  TOP_SHA => TOP_SHA,
1923  CON_VER => CON_VER,
1924  CON_SHA => CON_SHA,
1925  HOG_VER => HOG_VER,
1926  HOG_SHA => HOG_SHA,
1927 
1928  --IPBus XML
1929  XML_SHA => XML_SHA,
1930  XML_VER => XML_VER,
1931 
1932  ROD_EFEX_SHA => ROD_EFEX_SHA,
1933  ROD_EFEX_VER => ROD_EFEX_VER,
1934 
1935  jfex_rod => jfex_rod,
1936  efex_rod => efex_rod,
1937  golden_rod => golden_rod,
1938  --------------------------------------------------
1939  Module_ID => Module_ID,
1940 -- XmlVersion => XML_VER,
1941  BuildTimeAndDate => GLOBAL_DATE,
1942  FirmwareVersion => GLOBAL_SHA
1943  )
1944  port map (
1945  ipbr_backplane => ipbr_backplane,
1946  ipbw_backplane => ipbw_backplane,
1947  ipbr_Processor => ipbr_Processor,
1948  ipbw_Processor => ipbw_Processor,
1949  ipb_clk => ipb_clk,
1950  ipb_rst => ipb_rst,
1951 
1952  CLK_125 => CLK_125,
1953 
1954  gtx_clk_bufg_out => gtx_clk_bufg_out,
1955 
1956 
1957  phy_resetn => open,
1958 
1959  -- RGMII Interface
1960  ------------------
1961  rgmii_txd => rgmii_txd,
1962  rgmii_tx_ctl => rgmii_tx_ctl,
1963  rgmii_txc => rgmii_txc,
1964  rgmii_rxd => rgmii_rxd,
1965  rgmii_rx_ctl => rgmii_rx_ctl,
1966  rgmii_rxc => rgmii_rxc,
1967 
1968  -- MDIO Interface
1969  -----------------
1970  mdio => mdio,
1971  mdc => mdc,
1972  reset_error => reset_error,
1973 
1974  --LEDs
1975  -----------------
1976  leds => leds,
1977  userled => userled,
1978 
1979  --Rotary Switch
1980  --------------------
1981  rotary_switch => rotary_switch,
1982 
1983  -- GPIO Interface
1984  -------------------
1985  gp_button => '1',
1986  test1_2 => '0',
1987  test1_3 => '0',
1988  test1_4 => '0',
1989  test1_5 => '0',
1990  t_wrn_b => t_wrn_b,
1991  smbalert_b => smbalert_b,
1992  -- gpio2_tri_i(7) => ,
1993  -- gpio2_tri_i(8) => ,
1994  ck_pll_lock => ck_pll_lock,
1995  ck_int => ck_int,
1996  phy_int => phy_int,
1997  t_pod0_int => t_pod0_int,
1998  t_pod1_int => t_pod1_int,
1999  t_pod2_int => t_pod2_int,
2000  r_pod_int => r_pod_int,
2001  loc_addr1 => loc_addr1,
2002  loc_addr2 => loc_addr2,
2003  loc_addr3 => loc_addr3,
2004  loc_addr4 => loc_addr4,
2005  loc_addr5 => loc_addr5,
2006  loc_addr6 => loc_addr6,
2007  loc_addr7 => loc_addr7,
2008  loc_addr8 => loc_addr8,
2009 
2010 -- rod_gp_led => open,
2011 -- FP_GP_LED_B => open,
2012  FP_RUN_LED_B => open,
2013  lemo => open,
2014  -- gpio_tri_o(4) => ,
2015  pwr_con3 => open,
2016 -- pwr_con4 => pwr_con4,
2017  pwr_con4 => open,
2018  -- gpio_tri_o(7) => ,
2019  ck_pwr_dnb => open,
2020  ref_clk_sel => open,
2021  ck_syncb => open,
2022 -- phy_rst_n => open,
2023  t_pod0_rst_b => open,
2024  t_pod1_rst_b => open,
2025  t_pod2_rst_b => open,
2026  r_pod_rst_b => open,
2027 
2028  --Configuration Flash Interface
2029  ---------------------------------
2030  EMC_INTF_addr => EMC_INTF_addr,
2031  EMC_INTF_ce_n => EMC_INTF_ce_n,
2032  EMC_INTF_oen => EMC_INTF_oen,
2033  EMC_INTF_wen => EMC_INTF_wen,
2034  emc_intf_dq_io => emc_intf_dq_io,
2035 
2036  --I2C 1,0 interface
2037  ----------------------------------
2038  iic_1_scl_io => iic_1_scl_io,
2039  iic_1_sda_io => iic_1_sda_io,
2040  iic_scl_io => iic_scl_io,
2041  iic_sda_io => iic_sda_io,
2042 
2043  --SPI Interface
2044  ------------------------------------
2045  CK_SPI_MOSI => CK_SPI_MOSI,
2046  CK_SPI_MISO => CK_SPI_MISO,
2047  CK_SPI_CK => CK_SPI_CK,
2048 -- CK_SPI_LE => CK_SPI_LE,
2049  CK_SPI_LE => open,
2050 
2051 
2052  --XADC interface
2053  --------------------------------------
2054  Vp_Vn_v_n => Vp_Vn_v_n,
2055  Vp_Vn_v_p => Vp_Vn_v_p
2056 
2057  );
2058 
2059 
2060 
2061  geo_location(0) <= loc_addr1;
2062  geo_location(1) <= loc_addr2;
2063  geo_location(2) <= loc_addr3;
2064  geo_location(3) <= loc_addr4;
2065  geo_location(4) <= loc_addr5;
2066  geo_location(5) <= loc_addr6;
2067  geo_location(6) <= loc_addr7;
2068  geo_location(7) <= loc_addr8;
2069 
2070 
2071  backplane : aurora_64b_rx_12ch
2072  port map (
2073 
2074  pp_clock => pp_clock,
2075  clk_160 => clk_160,
2076  backplane_control => backplane_control,
2077 
2078  cttc_cpllpd_in => cttc_cpllpd_in,
2079  cttc_rxbufreset_in => cttc_rxbufreset_in,
2080  cttc_rxpcsreset_in => cttc_rxpcsreset_in,
2081  cttc_rxpmareset_in => cttc_rxpmareset_in,
2082  cttc_rxcdrhold_in => cttc_rxcdrhold_in,
2083  cttc_rxpd_in => cttc_rxpd_in,
2084 
2085 
2086 
2087  init_clk => CLK_125,
2088  GT_RESET_IN => '0',
2089  RESET => '0',
2090  vio_chan_reset => vio_chan_reset,
2091  sys_top_reset => sys_top_reset,
2092 
2093 
2094 
2095  GTCLK_q112_c0p => GTCLK_q112_c0p,
2096  GTCLK_q112_c0n => GTCLK_q112_c0n,
2097  GTCLK_q115_c0p => GTCLK_q115_c0p,
2098  GTCLK_q115_c0n => GTCLK_q115_c0n,
2099 
2100  GTCLK_q118_c0p => GTCLK_q118_c0p,
2101  GTCLK_q118_c0n => GTCLK_q118_c0n,
2102 
2103  GTCLK_q211_c0p => GTCLK_q211_c0p,
2104  GTCLK_q211_c0n => GTCLK_q211_c0n,
2105 
2106  GTCLK_q214_c0p => GTCLK_q214_c0p,
2107  GTCLK_q214_c0n => GTCLK_q214_c0n,
2108 
2109  GTCLK_q217_c0p => GTCLK_q217_c0p,
2110  GTCLK_q217_c0n => GTCLK_q217_c0n,
2111 
2112 -- GTCLK_q219_c0p => GTCLK_q219_c0p,
2113 -- GTCLK_q219_c0n => GTCLK_q219_c0n,
2114  gt_refclk_q219_c0 => gt_refclk_q219_c0,
2115 
2116 -----aurora slot 3 ----------------
2117  RXP_3 => RXP_3,
2118  RXN_3 => RXN_3,
2119 
2120 
2121  CHANNEL_STAT_3 => CHANNEL_STAT_3,
2122  CHANNEL_CTRL_3 => CHANNEL_CTRL_3,
2123 
2124  m_axi_rx_tdata_3 => m_axi_rx_tdata_3,
2125  m_axi_rx_tvalid_3 => m_axi_rx_tvalid_3,
2126  m_axi_rx_tlast_3 => m_axi_rx_tlast_3,
2127  -- User Flow Control RX Inteface
2128  m_axi_ufc_rx_tdata_3 => m_axi_ufc_rx_tdata_3,
2129  m_axi_ufc_rx_tvalid_3 => m_axi_ufc_rx_tvalid_3,
2130  m_axi_ufc_rx_tlast_3 => m_axi_ufc_rx_tlast_3,
2131  USER_CLK_OUT_3 => user_clk_out_3,
2132 ------------------------------------------------
2133 -- Aurora slot 4 ---------------------
2134  RXP_4 => RXP_4,
2135  RXN_4 => RXN_4,
2136  USER_CLK_OUT_4 => user_clk_out_4,
2137  CHANNEL_STAT_4 => CHANNEL_STAT_4,
2138  CHANNEL_CTRL_4 => CHANNEL_CTRL_4,
2139  m_axi_rx_tdata_4 => m_axi_rx_tdata_4,
2140  m_axi_rx_tkeep_4 => m_axi_rx_tkeep_4,
2141  m_axi_rx_tvalid_4 => m_axi_rx_tvalid_4,
2142  m_axi_rx_tlast_4 => m_axi_rx_tlast_4,
2143 
2144 
2145  -- User Flow Control RX Inteface
2146  m_axi_ufc_rx_tdata_4 => m_axi_ufc_rx_tdata_4,
2147  m_axi_ufc_rx_tvalid_4 => m_axi_ufc_rx_tvalid_4,
2148  m_axi_ufc_rx_tlast_4 => m_axi_ufc_rx_tlast_4,
2149 
2150 
2151 
2152 
2153 ---- Aurora 5 ----------------------
2154 -- Aurora slot 5 ---------------------
2155  RXP_5 => RXP_5,
2156  RXN_5 => RXN_5,
2157  USER_CLK_OUT_5 => user_clk_out_5,
2158  CHANNEL_STAT_5 => CHANNEL_STAT_5,
2159  CHANNEL_CTRL_5 => CHANNEL_CTRL_5,
2160  m_axi_rx_tdata_5 => m_axi_rx_tdata_5,
2161  m_axi_rx_tvalid_5 => m_axi_rx_tvalid_5,
2162  m_axi_rx_tlast_5 => m_axi_rx_tlast_5,
2163 
2164  -- User Flow Control RX Inteface
2165  m_axi_ufc_rx_tdata_5 => m_axi_ufc_rx_tdata_5,
2166  m_axi_ufc_rx_tvalid_5 => m_axi_ufc_rx_tvalid_5,
2167  m_axi_ufc_rx_tlast_5 => m_axi_ufc_rx_tlast_5,
2168 
2169 
2170 
2171 ------------------------------------------------------
2172 -- Aurora slot 6 ---------------------
2173  RXP_6 => RXP_6,
2174  RXN_6 => RXN_6,
2175  USER_CLK_OUT_6 => user_clk_out_6,
2176  CHANNEL_STAT_6 => CHANNEL_STAT_6,
2177  CHANNEL_CTRL_6 => CHANNEL_CTRL_6,
2178  m_axi_rx_tdata_6 => m_axi_rx_tdata_6,
2179  m_axi_rx_tvalid_6 => m_axi_rx_tvalid_6,
2180  m_axi_rx_tlast_6 => m_axi_rx_tlast_6,
2181 
2182  -- User Flow Control RX Inteface
2183  m_axi_ufc_rx_tdata_6 => m_axi_ufc_rx_tdata_6,
2184  m_axi_ufc_rx_tvalid_6 => m_axi_ufc_rx_tvalid_6,
2185  m_axi_ufc_rx_tlast_6 => m_axi_ufc_rx_tlast_6,
2186 
2187 
2188 --Aurora_7 -------------------------------------------
2189  RXP_7 => RXP_7,
2190  RXN_7 => RXN_7,
2191  USER_CLK_OUT_7 => user_clk_out_7,
2192  CHANNEL_STAT_7 => CHANNEL_STAT_7,
2193  CHANNEL_CTRL_7 => CHANNEL_CTRL_7,
2194  m_axi_rx_tdata_7 => m_axi_rx_tdata_7,
2195  m_axi_rx_tvalid_7 => m_axi_rx_tvalid_7,
2196  m_axi_rx_tlast_7 => m_axi_rx_tlast_7,
2197 
2198  -- User Flow Control RX Inteface
2199  m_axi_ufc_rx_tdata_7 => m_axi_ufc_rx_tdata_7,
2200  m_axi_ufc_rx_tvalid_7 => m_axi_ufc_rx_tvalid_7,
2201  m_axi_ufc_rx_tlast_7 => m_axi_ufc_rx_tlast_7,
2202 
2203 
2204 --Aurora_8 -------------------------------------------
2205  RXP_8 => RXP_8,
2206  RXN_8 => RXN_8,
2207  USER_CLK_OUT_8 => user_clk_out_8,
2208  CHANNEL_STAT_8 => CHANNEL_STAT_8,
2209  CHANNEL_CTRL_8 => CHANNEL_CTRL_8,
2210  m_axi_rx_tdata_8 => m_axi_rx_tdata_8,
2211  m_axi_rx_tvalid_8 => m_axi_rx_tvalid_8,
2212  m_axi_rx_tlast_8 => m_axi_rx_tlast_8,
2213 
2214  -- User Flow Control RX Inteface
2215  m_axi_ufc_rx_tdata_8 => m_axi_ufc_rx_tdata_8,
2216  m_axi_ufc_rx_tvalid_8 => m_axi_ufc_rx_tvalid_8,
2217  m_axi_ufc_rx_tlast_8 => m_axi_ufc_rx_tlast_8,
2218 
2219 
2220 
2221 --Aurora_9 -------------------------------------------
2222  RXP_9 => RXP_9,
2223  RXN_9 => RXN_9,
2224  USER_CLK_OUT_9 => user_clk_out_9,
2225  CHANNEL_STAT_9 => CHANNEL_STAT_9,
2226  CHANNEL_CTRL_9 => CHANNEL_CTRL_9,
2227  m_axi_rx_tdata_9 => m_axi_rx_tdata_9,
2228  m_axi_rx_tvalid_9 => m_axi_rx_tvalid_9,
2229  m_axi_rx_tlast_9 => m_axi_rx_tlast_9,
2230 
2231  -- User Flow Control RX Inteface
2232  m_axi_ufc_rx_tdata_9 => m_axi_ufc_rx_tdata_9,
2233  m_axi_ufc_rx_tvalid_9 => m_axi_ufc_rx_tvalid_9,
2234  m_axi_ufc_rx_tlast_9 => m_axi_ufc_rx_tlast_9,
2235 
2236 
2237 
2238 
2239 ---Aurora_10-----------------------------------------
2240  RXP_10 => RXP_10,
2241  RXN_10 => RXN_10,
2242  USER_CLK_OUT_10 => user_clk_out_10,
2243  CHANNEL_STAT_10 => CHANNEL_STAT_10,
2244  CHANNEL_CTRL_10 => CHANNEL_CTRL_10,
2245  m_axi_rx_tdata_10 => m_axi_rx_tdata_10,
2246  m_axi_rx_tvalid_10 => m_axi_rx_tvalid_10,
2247  m_axi_rx_tlast_10 => m_axi_rx_tlast_10,
2248 
2249  -- User Flow Control RX Inteface
2250  m_axi_ufc_rx_tdata_10 => m_axi_ufc_rx_tdata_10,
2251  m_axi_ufc_rx_tvalid_10 => m_axi_ufc_rx_tvalid_10,
2252  m_axi_ufc_rx_tlast_10 => m_axi_ufc_rx_tlast_10,
2253 
2254 
2255 
2256 --Aurora_11 -------------------------------------------
2257  RXP_11 => RXP_11,
2258  RXN_11 => RXN_11,
2259  USER_CLK_OUT_11 => user_clk_out_11,
2260  CHANNEL_STAT_11 => CHANNEL_STAT_11,
2261  CHANNEL_CTRL_11 => CHANNEL_CTRL_11,
2262  m_axi_rx_tdata_11 => m_axi_rx_tdata_11,
2263  m_axi_rx_tvalid_11 => m_axi_rx_tvalid_11,
2264  m_axi_rx_tlast_11 => m_axi_rx_tlast_11,
2265 
2266  -- User Flow Control RX Inteface
2267  m_axi_ufc_rx_tdata_11 => m_axi_ufc_rx_tdata_11,
2268  m_axi_ufc_rx_tvalid_11 => m_axi_ufc_rx_tvalid_11,
2269  m_axi_ufc_rx_tlast_11 => m_axi_ufc_rx_tlast_11,
2270 
2271 
2272 
2273 ---Aurora_12-----------------------------------------
2274  RXP_12 => RXP_12,
2275  RXN_12 => RXN_12,
2276  USER_CLK_OUT_12 => user_clk_out_12,
2277  CHANNEL_STAT_12 => CHANNEL_STAT_12,
2278  CHANNEL_CTRL_12 => CHANNEL_CTRL_12,
2279  m_axi_rx_tdata_12 => m_axi_rx_tdata_12,
2280  m_axi_rx_tvalid_12 => m_axi_rx_tvalid_12,
2281  m_axi_rx_tlast_12 => m_axi_rx_tlast_12,
2282 
2283  -- User Flow Control RX Inteface
2284  m_axi_ufc_rx_tdata_12 => m_axi_ufc_rx_tdata_12,
2285  m_axi_ufc_rx_tvalid_12 => m_axi_ufc_rx_tvalid_12,
2286  m_axi_ufc_rx_tlast_12 => m_axi_ufc_rx_tlast_12,
2287 
2288 
2289 
2290 --Aurora_13 -------------------------------------------
2291  RXP_13 => RXP_13,
2292  RXN_13 => RXN_13,
2293  USER_CLK_OUT_13 => user_clk_out_13,
2294  CHANNEL_STAT_13 => CHANNEL_STAT_13,
2295  CHANNEL_CTRL_13 => CHANNEL_CTRL_13,
2296  m_axi_rx_tdata_13 => m_axi_rx_tdata_13,
2297  m_axi_rx_tvalid_13 => m_axi_rx_tvalid_13,
2298  m_axi_rx_tlast_13 => m_axi_rx_tlast_13,
2299  -- User Flow Control RX Inteface
2300  m_axi_ufc_rx_tdata_13 => m_axi_ufc_rx_tdata_13,
2301  m_axi_ufc_rx_tvalid_13 => m_axi_ufc_rx_tvalid_13,
2302  m_axi_ufc_rx_tlast_13 => m_axi_ufc_rx_tlast_13,
2303 
2304 
2305 
2306 --Aurora_14-----------------------------------------
2307  RXP_14 => RXP_14,
2308  RXN_14 => RXN_14,
2309  USER_CLK_OUT_14 => user_clk_out_14,
2310  CHANNEL_STAT_14 => CHANNEL_STAT_14,
2311  CHANNEL_CTRL_14 => CHANNEL_CTRL_14,
2312  m_axi_rx_tdata_14 => m_axi_rx_tdata_14,
2313  m_axi_rx_tvalid_14 => m_axi_rx_tvalid_14,
2314  m_axi_rx_tlast_14 => m_axi_rx_tlast_14,
2315 
2316  -- User Flow Control RX Inteface
2317  m_axi_ufc_rx_tdata_14 => m_axi_ufc_rx_tdata_14,
2318  m_axi_ufc_rx_tvalid_14 => m_axi_ufc_rx_tvalid_14,
2319  m_axi_ufc_rx_tlast_14 => m_axi_ufc_rx_tlast_14,
2320 
2321 
2322 
2323 ----readout_ctrl specific
2324  RO_CTRL_TXN => RO_CTRL_TXN,
2325  RO_CTRL_TXP => RO_CTRL_TXP,
2326 
2327  DRP_CLK_IN => CLK_40,
2328  MASTER_RESET => MASTER_RESET,
2329  SW2 => gp_button_i,
2330 
2331 
2332  ro_user_clock => ro_user_clock,
2333  ro_controller_reset => ro_controller_reset,
2334  ro_txcharisk => ro_txcharisk,
2335  ro_txdata => ro_txdata,
2336  ro_status => ro_status,
2337 
2338 
2339 
2340 --combined_TTC
2341  ttc_RXP => RXP_ttc,
2342  ttc_RXN => RXN_ttc,
2343  ttc_word_0 => ttc_word_0,
2344  ttc_word_1 => ttc_word_1,
2345  ttc_word_2 => ttc_word_2,
2346  ttc_word_3 => ttc_word_3,
2347  ttc_seq => ttc_seq,
2348  cttc_usrclk => cttc_usrclk,
2349  ttc_status => ttc_status,
2350  ttc_reset => ttc_reset,
2351 
2352  --------------------------ttc ports -----------------------------
2353  BP_CTTC_rxdata => BP_CTTC_rxdata,
2354  BP_CTTC_rxcharisk => BP_CTTC_rxcharisk,
2355  BP_CTTC_MGT_bus => BP_CTTC_MGT_bus,
2356  BP_CTTC_rxoutclk => BP_CTTC_rxoutclk
2357 
2358  );
2359 
2360 --
2361 --
2362 
2363 --ILA_axi_slot3 : axi_ch0
2364 -- PORT MAP (
2365 -- clk => user_clk_out_3,
2366 -- probe0 => m_axi_rx_tdata_3,
2367 -- probe1(0) => m_axi_rx_tvalid_3,
2368 -- probe2(0) => m_axi_rx_tlast_3,
2369 -- probe3(0) => CHANNEL_STAT_3(0)
2370 -- );
2371 
2372 --ILA_axi_slot4 : axi_ch0
2373 -- PORT MAP (
2374 -- clk => user_clk_out_4,
2375 -- probe0 => m_axi_rx_tdata_4,
2376 -- probe1(0) => m_axi_rx_tvalid_4,
2377 -- probe2(0) => m_axi_rx_tlast_4,
2378 -- probe3(0) => CHANNEL_STAT_4(0),
2379 -- probe4(0) => CHANNEL_STAT_4(10)
2380 -- );
2381 
2382 
2383 ILA_axi_chan_0 : fex_rx_checker
2384 
2385  Port map (
2386  clock => user_clk_out_13,
2387  reset => backplane_control(1),
2388  tvalid => m_axi_rx_tvalid_13,
2389  tlast => m_axi_rx_tlast_13,
2390  tdata => m_axi_rx_tdata_13,
2391  channel_up => CHANNEL_STAT_13(0),
2392  soft_error => CHANNEL_STAT_13(9),
2393  hard_error => CHANNEL_STAT_13(8),
2394  L1A => L1A,
2395  l1id_mis_stretch => l1id_mis_stretch
2396  );
2397 
2398 ILA_axi_chan_6 : fex_rx_checker
2399 
2400  Port map (
2401  clock => user_clk_out_4,
2402  reset => backplane_control(1),
2403  tvalid => m_axi_rx_tvalid_4,
2404  tlast => m_axi_rx_tlast_4,
2405  tdata => m_axi_rx_tdata_4,
2406  channel_up => CHANNEL_STAT_4(0),
2407  soft_error => CHANNEL_STAT_4(9),
2408  hard_error => CHANNEL_STAT_4(8),
2409  L1A => L1A,
2410  l1id_mis_stretch => l1id_mis_stretch
2411  );
2412 
2413 --ILA_full_aurora_probe_4 : ila_full_aurora
2414 -- PORT MAP (
2415 -- clk => user_clk_out_4,
2416 -- probe0 => m_axi_rx_tdata_4,
2417 -- probe1(0) => m_axi_rx_tvalid_4,
2418 -- probe2(0) => m_axi_rx_tlast_4,
2419 -- probe3 => m_axi_rx_tkeep_4,
2420 -- probe4 => CHANNEL_STAT_4,
2421 -- probe5 => channel_CTRL_4
2422 --);
2423 
2424 
2425 
2426 
2427 
2428 
2429 
2430 
2431 slot5_dbg: if debug=1 generate
2432 ILA_axi_slot5 : axi_ch0
2433  PORT MAP (
2434  clk => user_clk_out_5,
2435  probe0 => m_axi_rx_tdata_5,
2436  probe1(0) => m_axi_rx_tvalid_5,
2437  probe2(0) => m_axi_rx_tlast_5,
2438  probe3(0) => CHANNEL_STAT_5(0),
2439  probe4(0) => CHANNEL_STAT_5(10)
2440  );
2441 end generate slot5_dbg;
2442 
2443 
2444 
2445 
2446 pp_ctrl_dbg: if debug=1 generate
2447 vio_pp_ctrl : pp_ctrl_vio
2448  PORT MAP (
2449  clk => pp_clock,
2450  probe_out0(11 downto 0) => channel_enable_vio(11 downto 0),
2451  probe_out1 => first_chan_vio,
2452  probe_out2 => last_chan_vio,
2453  probe_out3(0) => TTC_ignore_vio,
2454  probe_out4(0) => pp_soft_reset_vio,
2455  probe_out5(0) => debug_ctrl_vio
2456  );
2457 end generate pp_ctrl_dbg;
2458 
2459 pp_ctrl_wired: if debug=0 generate
2460 channel_enable_vio <= (others => '0');
2461 first_chan_vio <= (others => '0');
2462 last_chan_vio <= (others => '0');
2463 TTC_ignore_vio <= ('0');
2464 pp_soft_reset_vio <= ('0');
2465 debug_ctrl_vio <= ('0');
2466 end generate pp_ctrl_wired;
2467 
2468 
2469 -- pkt_areset <= not pkt_ARESETN;
2470 
2471 pp_reset <= sys_top_reset OR pp_soft_reset_vio;
2472 
2473 
2474 
2475  event_builder : packet_processor
2476  generic map (sim => 0,
2477  jfex => jfex_rod,
2478  CRC20_G_Poly => CRC20_G_Poly,
2479  tob_0_flx_bp_link => tob_0_flx_bp_link,
2480  bulk_0_flx_bp_link => bulk_0_flx_bp_link,
2481  bulk_1_flx_bp_link => bulk_1_flx_bp_link,
2482  bulk_2_flx_bp_link => bulk_2_flx_bp_link
2483  )
2484 
2485  port map (
2486  ipb_clk => ipb_clk,
2487  ipb_rst => ipb_rst,
2488 
2489  ipb_in_backplane => ipbw_backplane,
2490  ipb_out_backplane => ipbr_backplane,
2491 
2492  ipb_in_processor => ipbw_Processor,
2493  ipb_out_processor => ipbr_Processor,
2494 
2495  geo_location => geo_location,
2496  L1A => open,
2497  L1A_delay_out => L1A,
2498  l1id_mis_stretch => l1id_mis_stretch,
2499  full_mode_stat_tob_0 => full_mode_stat_tob_0,
2500  full_mode_stat_bulk_0 => full_mode_stat_bulk_0,
2501  full_mode_stat_bulk_1 => full_mode_stat_bulk_1,
2502  full_mode_stat_bulk_2 => full_mode_stat_bulk_2,
2503 
2504  FM_L1id_stat_tob_0 => FM_L1id_stat_tob_0,
2505  FM_L1id_stat_bulk_0 => FM_L1id_stat_bulk_0,
2506  FM_L1id_stat_bulk_1 => FM_L1id_stat_bulk_1,
2507  FM_L1id_stat_bulk_2 => FM_L1id_stat_bulk_2,
2508 
2509  full_mode_ctrl_tob_0 => full_mode_ctrl_tob_0,
2510  full_mode_ctrl_bulk_0 => full_mode_ctrl_bulk_0,
2511  full_mode_ctrl_bulk_1 => full_mode_ctrl_bulk_1,
2512  full_mode_ctrl_bulk_2 => full_mode_ctrl_bulk_2,
2513 
2514  stage_fifo_level_tob_0 => stage_fifo_level_tob_0(15 downto 0),
2515  stage_fifo_level_bulk_0 => stage_fifo_level_bulk_0(15 downto 0),
2516  stage_fifo_level_bulk_1 => stage_fifo_level_bulk_1(15 downto 0),
2517  stage_fifo_level_bulk_2 => stage_fifo_level_bulk_2(15 downto 0),
2518 
2519  stage_fifo_busy_tob_0 => stage_fifo_busy_tob_0,
2520  stage_fifo_xoff_tob_0 => open,
2521  stage_fifo_full_tob_0 => stage_fifo_full_tob_0,
2522  flx_backpressure_tob_0 => flx_backpressure_tob_0,
2523 
2524 
2525  stage_fifo_busy_bulk_0 => stage_fifo_busy_bulk_0,
2526  stage_fifo_xoff_bulk_0 => open,
2527  stage_fifo_full_bulk_0 => stage_fifo_full_bulk_0,
2528  flx_backpressure_bulk_0 => flx_backpressure_bulk_0,
2529 
2530 
2531  stage_fifo_busy_bulk_1 => stage_fifo_busy_bulk_1,
2532  stage_fifo_xoff_bulk_1 => open,
2533  stage_fifo_full_bulk_1 => stage_fifo_full_bulk_1,
2534  flx_backpressure_bulk_1 => flx_backpressure_bulk_1,
2535 
2536 
2537  stage_fifo_busy_bulk_2 => stage_fifo_busy_bulk_2,
2538  stage_fifo_xoff_bulk_2 => open,
2539  stage_fifo_full_bulk_2 => stage_fifo_full_bulk_2,
2540  flx_backpressure_bulk_2 => flx_backpressure_bulk_2,
2541 
2542 
2543  pp_clock => pp_clock,
2544  clk_40 => clk_40,
2545  backplane_control => backplane_control,
2546  clk_160 => clk_160,
2547 
2548 
2549  -- rt_clk => pp_clock,
2550  rt_clk => clk_40,
2551  -------------------------------------------------------
2552 
2553 
2554  init_clk => clk_125,
2555  master_reset => master_reset,
2556  rod_slot => geo_location(0),
2557  ck_pll_lock => ck_pll_lock,
2558 
2559  CK_INT => CK_INT,
2560  SMBALERT_B => SMBALERT_B,
2561  T_WRN_B => T_WRN_B,
2562 -- clk_40 => clk_40,
2563 -- RESET => pkt_ARESET,
2564 -- RESET => sys_top_reset,
2565  System_RESET => pp_reset,
2566 
2567  flx_backpressure => flx_bp_bus,
2568 --readout controller
2569  ro_user_clock => ro_user_clock,
2570  ro_controller_reset => ro_controller_reset,
2571  ro_txcharisk => ro_txcharisk,
2572  ro_txdata => ro_txdata,
2573  ro_status => ro_status,
2574 
2575 
2576 ------------------AURORA CLOCKS--------------
2577 -- ROD Channel # => ATCA Logical slot connection
2578  aurora_user_clock_0 => user_clk_out_13,
2579  aurora_user_clock_1 => user_clk_out_11,
2580  aurora_user_clock_2 => user_clk_out_9,
2581  aurora_user_clock_3 => user_clk_out_7,
2582  aurora_user_clock_4 => user_clk_out_5,
2583  aurora_user_clock_5 => user_clk_out_3,
2584  aurora_user_clock_6 => user_clk_out_4,
2585  aurora_user_clock_7 => user_clk_out_6,
2586  aurora_user_clock_8 => user_clk_out_8,
2587  aurora_user_clock_9 => user_clk_out_10,
2588  aurora_user_clock_10 => user_clk_out_12,
2589  aurora_user_clock_11 => user_clk_out_14,
2590 
2591 
2592 
2593 
2594 
2595  bp_data_0 => m_axi_rx_tdata_13,
2596  bp_data_1 => m_axi_rx_tdata_11,
2597  bp_data_2 => m_axi_rx_tdata_9,
2598  bp_data_3 => m_axi_rx_tdata_7,
2599  bp_data_4 => m_axi_rx_tdata_5,
2600  bp_data_5 => m_axi_rx_tdata_3,
2601  bp_data_6 => m_axi_rx_tdata_4,
2602  bp_data_7 => m_axi_rx_tdata_6,
2603  bp_data_8 => m_axi_rx_tdata_8,
2604  bp_data_9 => m_axi_rx_tdata_10,
2605  bp_data_10 => m_axi_rx_tdata_12,
2606  bp_data_11 => m_axi_rx_tdata_14,
2607 
2608  s_axis_tvalid_0 => m_axi_rx_tvalid_13,
2609  s_axis_tvalid_1 => m_axi_rx_tvalid_11,
2610  s_axis_tvalid_2 => m_axi_rx_tvalid_9,
2611  s_axis_tvalid_3 => m_axi_rx_tvalid_7,
2612  s_axis_tvalid_4 => m_axi_rx_tvalid_5,
2613  s_axis_tvalid_5 => m_axi_rx_tvalid_3,
2614  s_axis_tvalid_6 => m_axi_rx_tvalid_4,
2615  s_axis_tvalid_7 => m_axi_rx_tvalid_6,
2616  s_axis_tvalid_8 => m_axi_rx_tvalid_8,
2617  s_axis_tvalid_9 => m_axi_rx_tvalid_10,
2618  s_axis_tvalid_10 => m_axi_rx_tvalid_12,
2619  s_axis_tvalid_11 => m_axi_rx_tvalid_14,
2620 
2621  s_axis_tlast_0 => m_axi_rx_tlast_13,
2622  s_axis_tlast_1 => m_axi_rx_tlast_11,
2623  s_axis_tlast_2 => m_axi_rx_tlast_9,
2624  s_axis_tlast_3 => m_axi_rx_tlast_7,
2625  s_axis_tlast_4 => m_axi_rx_tlast_5,
2626  s_axis_tlast_5 => m_axi_rx_tlast_3,
2627  s_axis_tlast_6 => m_axi_rx_tlast_4,
2628  s_axis_tlast_7 => m_axi_rx_tlast_6,
2629  s_axis_tlast_8 => m_axi_rx_tlast_8,
2630  s_axis_tlast_9 => m_axi_rx_tlast_10,
2631  s_axis_tlast_10 => m_axi_rx_tlast_12,
2632  s_axis_tlast_11 => m_axi_rx_tlast_14,
2633 
2634  s_axis_tready_0 => open,
2635  s_axis_tready_1 => open,
2636  s_axis_tready_2 => open,
2637  s_axis_tready_3 => open,
2638  s_axis_tready_4 => open,
2639  s_axis_tready_5 => open,
2640  s_axis_tready_6 => open,
2641  s_axis_tready_7 => open,
2642  s_axis_tready_8 => open,
2643  s_axis_tready_9 => open,
2644  s_axis_tready_10 => open,
2645  s_axis_tready_11 => open,
2646 
2647  s_axi_ufc_rx_tdata_0 => m_axi_ufc_rx_tdata_13,
2648  s_axi_ufc_rx_tdata_1 => m_axi_ufc_rx_tdata_11,
2649  s_axi_ufc_rx_tdata_2 => m_axi_ufc_rx_tdata_9,
2650  s_axi_ufc_rx_tdata_3 => m_axi_ufc_rx_tdata_7,
2651  s_axi_ufc_rx_tdata_4 => m_axi_ufc_rx_tdata_5,
2652  s_axi_ufc_rx_tdata_5 => m_axi_ufc_rx_tdata_3,
2653  s_axi_ufc_rx_tdata_6 => m_axi_ufc_rx_tdata_4,
2654  s_axi_ufc_rx_tdata_7 => m_axi_ufc_rx_tdata_6,
2655  s_axi_ufc_rx_tdata_8 => m_axi_ufc_rx_tdata_8,
2656  s_axi_ufc_rx_tdata_9 => m_axi_ufc_rx_tdata_10,
2657  s_axi_ufc_rx_tdata_10 => m_axi_ufc_rx_tdata_12,
2658  s_axi_ufc_rx_tdata_11 => m_axi_ufc_rx_tdata_14,
2659 
2660 
2661 
2662  s_axi_ufc_rx_tvalid_0 => m_axi_ufc_rx_tvalid_13,
2663  s_axi_ufc_rx_tvalid_1 => m_axi_ufc_rx_tvalid_11,
2664  s_axi_ufc_rx_tvalid_2 => m_axi_ufc_rx_tvalid_9,
2665  s_axi_ufc_rx_tvalid_3 => m_axi_ufc_rx_tvalid_7,
2666  s_axi_ufc_rx_tvalid_4 => m_axi_ufc_rx_tvalid_5,
2667  s_axi_ufc_rx_tvalid_5 => m_axi_ufc_rx_tvalid_3,
2668  s_axi_ufc_rx_tvalid_6 => m_axi_ufc_rx_tvalid_4,
2669  s_axi_ufc_rx_tvalid_7 => m_axi_ufc_rx_tvalid_6,
2670  s_axi_ufc_rx_tvalid_8 => m_axi_ufc_rx_tvalid_8,
2671  s_axi_ufc_rx_tvalid_9 => m_axi_ufc_rx_tvalid_10,
2672  s_axi_ufc_rx_tvalid_10 => m_axi_ufc_rx_tvalid_12,
2673  s_axi_ufc_rx_tvalid_11 => m_axi_ufc_rx_tvalid_14,
2674 
2675 
2676  s_axi_ufc_rx_tlast_0 => m_axi_ufc_rx_tlast_13,
2677  s_axi_ufc_rx_tlast_1 => m_axi_ufc_rx_tlast_11,
2678  s_axi_ufc_rx_tlast_2 => m_axi_ufc_rx_tlast_9,
2679  s_axi_ufc_rx_tlast_3 => m_axi_ufc_rx_tlast_7,
2680  s_axi_ufc_rx_tlast_4 => m_axi_ufc_rx_tlast_5,
2681  s_axi_ufc_rx_tlast_5 => m_axi_ufc_rx_tlast_3,
2682  s_axi_ufc_rx_tlast_6 => m_axi_ufc_rx_tlast_4,
2683  s_axi_ufc_rx_tlast_7 => m_axi_ufc_rx_tlast_6,
2684  s_axi_ufc_rx_tlast_8 => m_axi_ufc_rx_tlast_8,
2685  s_axi_ufc_rx_tlast_9 => m_axi_ufc_rx_tlast_10,
2686  s_axi_ufc_rx_tlast_10 => m_axi_ufc_rx_tlast_12,
2687  s_axi_ufc_rx_tlast_11 => m_axi_ufc_rx_tlast_14,
2688 
2689  multichannel_busy => multichannel_busy,
2690  combined_busy => combined_busy,
2691 
2692 
2693 
2694  channel_enable_vio => channel_enable_vio,
2695  first_chan_vio => first_chan_vio,
2696  last_chan_vio => last_chan_vio,
2697  TTC_ignore_vio => TTC_ignore_vio,
2698  debug_ctrl_vio => debug_ctrl_vio,
2699 
2700 --- output queue(s)
2701 
2702  m_tvalid_0 => pp0_m_axi_tvalid,
2703  m_tlast_0 => pp0_m_axi_tlast,
2704  m_tdata_0 => pp0_m_axi_tdata,
2705  m_header_marker_0 => open,
2706  m_tail_marker_0 => open,
2707  m_tready_0 => pp0_m_axi_tready,
2708 
2709 
2710  bulk_m_tvalid_0 => bulk_m_tvalid_0,
2711  bulk_m_tlast_0 => bulk_m_tlast_0,
2712  bulk_m_tdata_0 => bulk_m_tdata_0,
2713  bulk_m_header_marker_0 => bulk_m_header_marker_0,
2714  bulk_m_tail_marker_0 => bulk_m_tail_marker_0,
2715  bulk_m_tready_0 => bulk_m_tready_0,
2716 
2717 
2718  bulk_m_tvalid_1 => bulk_m_tvalid_1,
2719  bulk_m_tlast_1 => bulk_m_tlast_1,
2720  bulk_m_tdata_1 => bulk_m_tdata_1,
2721  bulk_m_header_marker_1 => bulk_m_header_marker_1,
2722  bulk_m_tail_marker_1 => bulk_m_tail_marker_1,
2723  bulk_m_tready_1 => bulk_m_tready_1,
2724 
2725  bulk_m_tvalid_2 => bulk_m_tvalid_2,
2726  bulk_m_tlast_2 => bulk_m_tlast_2,
2727  bulk_m_tdata_2 => bulk_m_tdata_2,
2728  bulk_m_header_marker_2 => bulk_m_header_marker_2,
2729  bulk_m_tail_marker_2 => bulk_m_tail_marker_2,
2730  bulk_m_tready_2 => bulk_m_tready_2,
2731 
2732 
2733 
2734 
2735 
2736 --TTC signals
2737  cttc_user_clk => cttc_usrclk,
2738  ttc_status => ttc_status,
2739  ttc_reset => ttc_reset,
2740  ttc_seq => ttc_seq,
2741  ttc_word_0 => ttc_word_0,
2742  ttc_word_1 => ttc_word_1,
2743  ttc_word_2 => ttc_word_2,
2744  ttc_word_3 => ttc_word_3,
2745 
2746 
2747  -- channel => logical slot
2748  aurora_chan_stat_0 => CHANNEL_STAT_13,
2749  aurora_chan_stat_1 => CHANNEL_STAT_11,
2750  aurora_chan_stat_2 => CHANNEL_STAT_9,
2751  aurora_chan_stat_3 => CHANNEL_STAT_7,
2752  aurora_chan_stat_4 => CHANNEL_STAT_5,
2753  aurora_chan_stat_5 => CHANNEL_STAT_3,
2754  aurora_chan_stat_6 => CHANNEL_STAT_4,
2755  aurora_chan_stat_7 => CHANNEL_STAT_6,
2756  aurora_chan_stat_8 => CHANNEL_STAT_8,
2757  aurora_chan_stat_9 => CHANNEL_STAT_10,
2758  aurora_chan_stat_10 => CHANNEL_STAT_12,
2759  aurora_chan_stat_11 => CHANNEL_STAT_14,
2760 
2761  aurora_chan_control_0 => CHANNEL_CTRL_13,
2762  aurora_chan_control_1 => CHANNEL_CTRL_11,
2763  aurora_chan_control_2 => CHANNEL_CTRL_9,
2764  aurora_chan_control_3 => CHANNEL_CTRL_7,
2765  aurora_chan_control_4 => CHANNEL_CTRL_5,
2766  aurora_chan_control_5 => CHANNEL_CTRL_3,
2767  aurora_chan_control_6 => CHANNEL_CTRL_4,
2768  aurora_chan_control_7 => CHANNEL_CTRL_6,
2769  aurora_chan_control_8 => CHANNEL_CTRL_8,
2770  aurora_chan_control_9 => CHANNEL_CTRL_10,
2771  aurora_chan_control_10 => CHANNEL_CTRL_12,
2772  aurora_chan_control_11 => CHANNEL_CTRL_14,
2773 
2774 
2775  ttc_mux_ctrl => ttc_mux_ctrl,
2776  BP_CTTC_rxdata => BP_CTTC_rxdata,
2777  FM_CTTC_rxdata => FM_CTTC_rxdata,
2778  BP_CTTC_rxcharisk => BP_CTTC_rxcharisk,
2779  FM_CTTC_rxcharisk => FM_CTTC_rxcharisk,
2780  BP_CTTC_MGT_bus => BP_CTTC_MGT_bus,
2781  FM_CTTC_MGT_bus => FM_CTTC_MGT_bus,
2782  BP_CTTC_rxoutclk => BP_CTTC_rxoutclk,
2783  FM_CTTC_rxoutclk => FM_CTTC_rxoutclk
2784 
2785  );
2786 
2787 
2788 ttc_source_sel : vio_ttc
2789  PORT MAP (
2790  clk => pp_clock,
2791  probe_in0(0) => '0',
2792  probe_out0(0) => ttc_mux_ctrl
2793  );
2794 
2795 
2796 
2797 
2798 --fm_soft_reset <= backplane_control(5) or backplane_control(6);
2799 fm_soft_reset <= backplane_control(6);
2800 
2801 fm_interface_1 : Full_Mode_Tx
2802 generic map ( debug => 0)
2803 port map (
2804 -- GTREFCLK0_N_IN => GTCLK_q218_c1n,
2805 -- GTREFCLK0_P_IN => GTCLK_q218_c1p,
2806  GTREFCLK0 => GTCLK_q218,
2807  pp_clock => pp_clock,
2808  RESET_BUTTON => '1',
2809 
2810  app_clk_in => CLK_40,
2811  gtrxn_in => "11",
2812  gtrxp_in => "00",
2813  gttxn_out => fm1_gttxn_out,
2814  gttxp_out => fm1_gttxp_out,
2815 
2816 
2817  s_axis_tvalid_0 => bulk_fm_tvalid_0,
2818  s_axis_tlast_0 => bulk_fm_tlast_0,
2819 
2820 --ready out from fm back to fifo connects to ready in on fifo
2821  s_axis_tready_0 => bulk_fm_tready_0,
2822  flx_bp_240_0 => flx_bp_240_bulk_0,
2823 
2824  s_axis_tdata_0 => bulk_fm_tdata_0,
2825  TXOUTCLK_0 => FM_TXOUTCLK,
2826  channel_reset_0 => master_reset,
2827  soft_reset_0 => fm_soft_reset,
2828  busy_0 => '0',
2829  --TestMode_0 => '0',
2830  interface_reset_0 => FM1_reset_0,
2831  full_mode_ctrl_0 => full_mode_ctrl_bulk_0,
2832  full_mode_stat_0 => full_mode_stat_bulk_0,
2833  FM_L1id_stat_0 => FM_L1id_stat_bulk_0,
2834 
2835 
2836  s_axis_tvalid_1 => bulk_fm_tvalid_2,
2837  s_axis_tlast_1 => bulk_fm_tlast_2,
2838  s_axis_tready_1 => bulk_fm_tready_2,
2839  flx_bp_240_1 => flx_bp_240_bulk_2,
2840  s_axis_tdata_1 => bulk_fm_tdata_2,
2841 -- TXOUTCLK_1 : out std_logic;
2842  channel_reset_1 => master_reset,
2843  soft_reset_1 => fm_soft_reset,
2844  busy_1 => '0',
2845  -- TestMode_1 => '0',
2846  interface_reset_1 => FM1_reset_1,
2847  full_mode_ctrl_1 => full_mode_ctrl_bulk_2,
2848  full_mode_stat_1 => full_mode_stat_bulk_2,
2849  FM_L1id_stat_1 => FM_L1id_stat_bulk_2
2850  );
2851 
2852 normal_cttc: if alt_cttc=0 generate
2853 
2854 fm_interface_2 : Full_Mode_Tx
2855  generic map ( debug => 0)
2856 port map (
2857 
2858  GTREFCLK0 => GTCLK_q218,
2859  RESET_BUTTON => '1',
2860  app_clk_in => CLK_40,
2861  pp_clock => pp_clock,
2862  gtrxn_in => "11",
2863  gtrxp_in => "00",
2864  gttxn_out => fm2_gttxn_out,
2865  gttxp_out => fm2_gttxp_out,
2866 --
2867 --
2868  s_axis_tvalid_0 => bulk_fm_tvalid_1,
2869  s_axis_tlast_0 => bulk_fm_tlast_1,
2870  s_axis_tready_0 => bulk_fm_tready_1,
2871  flx_bp_240_0 => flx_bp_240_bulk_1,
2872  s_axis_tdata_0 => bulk_fm_tdata_1,
2873  TXOUTCLK_0 => FM_TXOUTCLK_2,
2874  channel_reset_0 => master_reset,
2875  soft_reset_0 => fm_soft_reset,
2876  busy_0 => '0',
2877 -- TestMode_0 => '0',
2878  interface_reset_0 => FM2_reset_0,
2879  full_mode_ctrl_0 => full_mode_ctrl_bulk_1,
2880  full_mode_stat_0 => full_mode_stat_bulk_1,
2881  FM_L1id_stat_0 => FM_L1id_stat_bulk_1,
2882 --
2883  s_axis_tvalid_1 => ppout_fifo_AXI4_TVALID,
2884  s_axis_tlast_1 => ppout_fifo_AXI4_TLAST,
2885  s_axis_tready_1 => felix_ch1_AXI4_TREADY,
2886  flx_bp_240_1 => flx_bp_240_tob_0,
2887  s_axis_tdata_1 => ppout_fifo_AXI4_TDATA,
2888  channel_reset_1 => master_reset,
2889  soft_reset_1 => fm_soft_reset,
2890  busy_1 => combined_busy,
2891 -- TestMode_1 => '0',
2892  interface_reset_1 => FM2_reset_1,
2893  full_mode_ctrl_1 => full_mode_ctrl_tob_0,
2894  full_mode_stat_1 => full_mode_stat_tob_0,
2895  FM_L1id_stat_1 => FM_L1id_stat_tob_0
2896  );
2897 
2898 
2899 end generate normal_cttc;
2900 
2901 alternate_cttc: if alt_cttc=1 generate
2902  fm_interface_3 : Full_Mode_CTTC
2903  generic map ( debug => 0)
2904  port map (
2905 
2906  GTREFCLK0 => GTCLK_q218,
2907  pp_clock => pp_clock,
2908  RESET_BUTTON => '1',
2909  app_clk_in => CLK_40,
2910 -- gtrxn_in => "11",
2911 -- gtrxp_in => "00",
2912  gttxn_out => fm2_gttxn_out,
2913  gttxp_out => fm2_gttxp_out,
2914  --
2915  --
2916  s_axis_tvalid_0 => bulk_fm_tvalid_1,
2917  s_axis_tlast_0 => bulk_fm_tlast_1,
2918  s_axis_tready_0 => bulk_fm_tready_1,
2919  flx_bp_240_0 => flx_bp_240_bulk_1,
2920  s_axis_tdata_0 => bulk_fm_tdata_1,
2921  TXOUTCLK_0 => FM_TXOUTCLK_2,
2922  channel_reset_0 => master_reset,
2923  soft_reset_0 => fm_soft_reset,
2924  busy_0 => '0',
2925  -- TestMode_0 => '0',
2926  interface_reset_0 => FM2_reset_0,
2927 
2928  full_mode_ctrl_0 => full_mode_ctrl_bulk_1,
2929  full_mode_stat_0 => full_mode_stat_bulk_1,
2930  FM_L1id_stat_0 => FM_L1id_stat_bulk_1,
2931 
2932  --
2933  s_axis_tvalid_1 => ppout_fifo_AXI4_TVALID,
2934  s_axis_tlast_1 => ppout_fifo_AXI4_TLAST,
2935  s_axis_tready_1 => felix_ch1_AXI4_TREADY,
2936  flx_bp_240_1 => flx_bp_240_tob_0,
2937  s_axis_tdata_1 => ppout_fifo_AXI4_TDATA,
2938  channel_reset_1 => master_reset,
2939  soft_reset_1 => fm_soft_reset,
2940  busy_1 => combined_busy,
2941 -- TestMode_1 => '0',
2942  interface_reset_1 => FM2_reset_1,
2943  full_mode_ctrl_1 => full_mode_ctrl_tob_0,
2944  full_mode_stat_1 => full_mode_stat_tob_0,
2945  FM_L1id_stat_1 => FM_L1id_stat_tob_0,
2946  ------CTTC connections -------
2947 --***** CTTC PORTS ***********************************
2948  gt_refclk_q219_c0 => gt_refclk_q219_c0,
2949  -- Q9_CLK0_GTREFCLK_IN_P => GTCLK_q219_c0p, --Q9_CLK0_GTREFCLK_IN_P,
2950  -- Q9_CLK0_GTREFCLK_IN_N => GTCLK_q219_c0n, --Q9_CLK0_GTREFCLK_IN_N,
2951  DRP_CLK_IN => clk_40,
2952  gt0_rxusrclk => open,
2953  TRACK_DATA_OUT => open,
2954  ttc_word_0 => open,
2955  ttc_word_1 => open,
2956  ttc_word_2 => open,
2957  ttc_word_3 => open,
2958  ttc_seq => open,
2959  ttc_status => open,
2960  ttc_reset => ttc_reset,
2961  stop_ttc_info => backplane_control(29),
2962 
2963 
2964  cttc_cpllreset_in => '0',
2965  gt0_cpllpd_in => '0',
2966  gt0_rxbufreset_in => '0',
2967  gt0_rxpcsreset_in => '0',
2968  gt0_rxpmareset_in => '0',
2969  gt0_rxcdrhold_in => '0',
2970  gt0_rxpd_in => '0',
2971 
2972  CTTC_RXN_IN => CTTC_rxn_alt,
2973  CTTC_RXP_IN => CTTC_rxp_alt,
2974 
2975  FM_CTTC_rxdata => FM_CTTC_rxdata,
2976  FM_CTTC_rxcharisk => FM_CTTC_rxcharisk,
2977  FM_CTTC_MGT_bus => FM_CTTC_MGT_bus,
2978  FM_CTTC_rxoutclk => FM_CTTC_rxoutclk
2979  );
2980 
2981 end generate alternate_cttc;
2982 
2983 
2984 combined_busy <= multichannel_busy or stage_fifo_busy_tob_0 or stage_fifo_busy_bulk_0 or stage_fifo_busy_bulk_1 or stage_fifo_busy_bulk_2;
2985 
2986 LEMO_i <= not combined_busy;
2987 --LEMO_i <= combined_busy;
2988 
2989 
2990 Bulk_0_64_32 : packet_fifo
2991  Port map (
2992  --Slave (input) side
2993  s_axis_tdata => bulk_m_tdata_0,
2994  s_axis_tvalid => bulk_m_tvalid_0,
2995  s_axis_tlast => bulk_m_tlast_0,
2996 -- s_axis_tdata => (others => '0'),
2997 -- s_axis_tvalid => '0',
2998 -- s_axis_tlast => '0',
2999 
3000 
3001 
3002 --ready output back to bulk processor
3003  s_axis_tready => bulk_m_tready_0,
3004 
3005  --Master (output) side
3006  m_axis_tdata => bulk_fm_tdata_0,
3007  m_axis_tvalid => bulk_fm_tvalid_0,
3008  m_axis_tready => bulk_fm_TREADY_0,
3009 -- m_axis_tready => '1', --temp hack to get data moving through processor
3010  m_axis_tlast => bulk_fm_tlast_0,
3011 
3012  --control
3013 -- DATA_COUNT => open,
3014  WR_DATA_COUNT => stage_fifo_level_bulk_0,
3015 -- WR_DATA_COUNT(31 downto 16)=> open,
3016  RD_DATA_COUNT => open,
3017  fifo_full => stage_fifo_full_bulk_0,
3018 
3019  clk_160 => pp_clock,
3020 -- clk_160 => '0',
3021  clk_240 => FM_TXOUTCLK,
3022  RESET => FM1_reset_0,
3023 -- flx_backpressure => flx_bp_bus(bulk_0_flx_bp_link),
3024  flx_backpressure => flx_backpressure_bulk_0,
3025  flx_bp_enable => full_mode_ctrl_bulk_0(4),
3026  flx_bp_240 => flx_bp_240_bulk_0
3027 
3028  );
3029 
3030 Bulk_1_64_32 : packet_fifo
3031  Port map (
3032  --Slave (input) side
3033  s_axis_tdata => bulk_m_tdata_1,
3034  s_axis_tvalid => bulk_m_tvalid_1,
3035  s_axis_tlast => bulk_m_tlast_1,
3036 -- s_axis_tdata => (others => '0'),
3037 -- s_axis_tvalid => '0',
3038 -- s_axis_tlast => '0',
3039 
3040 
3041 
3042 --ready output back to bulk processor
3043  s_axis_tready => bulk_m_tready_1,
3044 
3045  --Master (output) side
3046  m_axis_tdata => bulk_fm_tdata_1,
3047  m_axis_tvalid => bulk_fm_tvalid_1,
3048  m_axis_tready => bulk_fm_TREADY_1,
3049  m_axis_tlast => bulk_fm_tlast_1,
3050 
3051  --control
3052  -- DATA_COUNT => open,
3053 -- WR_DATA_COUNT => open,
3054  WR_DATA_COUNT => stage_fifo_level_bulk_1,
3055 -- WR_DATA_COUNT(31 downto 16)=> open,
3056  RD_DATA_COUNT => open,
3057  fifo_full => stage_fifo_full_bulk_1,
3058  clk_160 => pp_clock,
3059 -- clk_160 => '0',
3060  clk_240 => FM_TXOUTCLK_2,
3061  RESET => FM2_reset_0,
3062 -- flx_backpressure => flx_bp_bus(bulk_1_flx_bp_link),
3063  flx_backpressure => flx_backpressure_bulk_1,
3064  flx_bp_enable => full_mode_ctrl_bulk_1(4),
3065  flx_bp_240 => flx_bp_240_bulk_1
3066 
3067  );
3068 
3069 Bulk_2_64_32 : packet_fifo
3070  Port map (
3071  --Slave (input) side
3072  s_axis_tdata => bulk_m_tdata_2,
3073  s_axis_tvalid => bulk_m_tvalid_2,
3074  s_axis_tlast => bulk_m_tlast_2,
3075 
3076 
3077 --ready output back to bulk processor
3078  s_axis_tready => bulk_m_tready_2,
3079 
3080  --Master (output) side
3081  m_axis_tdata => bulk_fm_tdata_2,
3082  m_axis_tvalid => bulk_fm_tvalid_2,
3083  m_axis_tready => bulk_fm_TREADY_2,
3084  m_axis_tlast => bulk_fm_tlast_2,
3085 
3086  --control
3087 
3088  WR_DATA_COUNT => stage_fifo_level_bulk_2,
3089  RD_DATA_COUNT => open,
3090  fifo_full => stage_fifo_full_bulk_2,
3091  clk_160 => pp_clock,
3092 -- clk_160 => '0',
3093  clk_240 => FM_TXOUTCLK,
3094  RESET => FM1_reset_1,
3095 -- flx_backpressure => flx_bp_bus(bulk_2_flx_bp_link),
3096  flx_backpressure => flx_backpressure_bulk_2,
3097  flx_bp_enable => full_mode_ctrl_bulk_2(4),
3098  flx_bp_240 => flx_bp_240_bulk_2
3099 
3100  );
3101 
3102 
3103 
3104 
3105 
3106 
3107 
3108 
3109 
3110 
3111 pp_out_fifo_6432 : packet_fifo
3112  Port map (
3113  --Slave (input) side
3114  s_axis_tdata => pp0_m_axi_tdata,
3115  s_axis_tvalid => pp0_m_axi_tvalid,
3116  s_axis_tlast => pp0_m_axi_tlast,
3117  s_axis_tready => pp0_m_axi_tready,
3118 
3119  --Master (output) side
3120  m_axis_tdata => ppout_fifo_AXI4_TDATA,
3121  m_axis_tvalid => ppout_fifo_AXI4_TVALID,
3122  m_axis_tready => felix_ch1_AXI4_TREADY,
3123  m_axis_tlast => ppout_fifo_AXI4_tlast,
3124 
3125  --control
3126 
3127  WR_DATA_COUNT => stage_fifo_level_tob_0,
3128  RD_DATA_COUNT => open,
3129  fifo_full => stage_fifo_full_tob_0,
3130  clk_160 => pp_clock,
3131  clk_240 => FM_TXOUTCLK_2,
3132  RESET => FM2_reset_1,
3133 -- flx_backpressure => flx_bp_bus(tob_0_flx_bp_link),
3134  flx_backpressure => flx_backpressure_tob_0,
3135  flx_bp_enable => full_mode_ctrl_tob_0(4),
3136  flx_bp_240 => flx_bp_240_tob_0
3137 
3138  );
3139 
3140 
3141 
3142 
3143 
3144  clk125_buf : IBUF
3145  port map (
3146  I => CLK_125_pin,
3147  O => CLK_125
3148  );
3149 
3150 --CLK40
3151 -- CLK_40_ibuf : IBUFGDS
3152  CLK_40_ibuf : IBUFDS
3153  port map
3154  (
3155  I => CLK_40_pin_P,
3156  IB => CLK_40_pin_N,
3157 -- O => CLK_40_pin
3158  O => CLK_40
3159  );
3160 
3161 -- CLK_40_g_buffer : BUFG
3162 -- port map
3163 -- (
3164 -- I => CLK_40_pin,
3165 -- O => CLK_40
3166 -- );
3167 
3168 
3169  spi_pwr: reset_count
3170  port map (
3171  clock => CLK_40,
3172  power_down_b => spi_pwr2
3173  );
3174 
3175 
3176  ck_pwr_dnb_buf : OBUF
3177  port map
3178  (
3179  I => spi_pwr2,
3180  O => CK_PWR_DNB
3181  );
3182 
3183 
3184  ck_spi_le_buf : OBUF
3185  port map
3186  (
3187  I => '1',
3188  O => CK_SPI_LE
3189 
3190  );
3191 
3192 
3193 
3194  ref_ck_sel_buf : OBUF
3195  port map
3196  (
3197  I => '1',
3198  O => REF_CLK_SEL
3199  );
3200 
3201  ck_syncb_buf : OBUF
3202  port map
3203  (
3204  I => '1',
3205  O => CK_SYNCB
3206  );
3207 
3208  pwr_con3_buf : OBUF
3209  port map
3210  (
3211  I => '1',
3212  O => PWR_CON3
3213  );
3214 
3215  pwr_con4_buf : OBUF
3216  port map
3217  (
3218  I => sys_top_reset,
3219  O => PWR_CON4
3220  );
3221 
3222  ibufds_q218 : IBUFDS_GTE2
3223  port map
3224  (
3225  O => GTCLK_q218,
3226  ODIV2 => open,
3227  CEB => '0',
3228  I => GTCLK_q218_c1p,
3229  IB => GTCLK_q218_c1n
3230  );
3231 
3232 
3233 
3234 --GP button test
3235  button_ibuf : IBUF
3236  port map (
3237  I => gp_button,
3238  O => gp_button_ibuf
3239  );
3240 
3241 gp_button_i <= not (not gp_button_ibuf or vio_reset or backplane_control(0));
3242 
3243 
3244 
3245 
3246 
3247  LEMO_obuf : OBUF
3248  port map
3249  (
3250  I => lemo_i,
3251  O => LEMO
3252  );
3253 
3254 IBUFDS_GTE2_q219_c0 : IBUFDS_GTE2
3255  port map (
3256  I => GTCLK_q219_c0p,
3257  IB => GTCLK_q219_c0n,
3258  CEB => '0',
3259  O => gt_refclk_q219_c0,
3260  ODIV2 => OPEN);
3261 
3262 
3263 
3264 --bkpln_cntl_dbg: if debug=1 generate
3265 --logical slot 5 is channel 4
3266 backplane_control_ila_5 : bkpln_control_ila
3267 PORT MAP (
3268  clk => user_clk_out_5,
3269  probe0(0) => Channel_ctrl_5(30),
3270  probe1(0) => Channel_ctrl_5(31),
3271  probe2 => CHANNEL_STAT_5
3272 );
3273 --channel 6 is slot 4 in the shelf
3274 backplane_control_ila_6 : bkpln_control_ila
3275 PORT MAP (
3276  clk => user_clk_out_6,
3277  probe0(0) => Channel_ctrl_6(30),
3278  probe1(0) => Channel_ctrl_6(31),
3279  probe2 => CHANNEL_STAT_6
3280 );
3281 
3282 --end generate bkpln_cntl_dbg;
3283 
3284 --slot_5_status_ila : backplane_control_ila
3285 --PORT MAP (
3286 -- clk => user_clk_out_5,
3287 -- probe0 => CHANNEL_STAT_5
3288 --);
3289 
3290 
3291 end RTL;
3292 
3293 
3294 
3295 
3296 
3297 
fex_rx_checker
Definition: fex_rx_checker.vhd:34
packet_fifo
Definition: packet_fifo.vhd:36
packet_processor
Definition: packet_processor.vhd:44
reset_count
Definition: reset_count.vhd:35
system_top_reset
Reset Timer.
Definition: system_top_reset.vhd:9
top_rod_efex.rtl
Definition: top_rod_efex.vhd:354
top_rod_efex
Definition: top_rod_efex.vhd:44
top_rod_efex.GLOBAL_VER
GLOBAL_VER std_logic_vector( 31 downto 0) := x"00000002"
Version of the repository (format: MMmmcccc in hex)
Definition: top_rod_efex.vhd:63
top_rod_efex.GLOBAL_TIME
GLOBAL_TIME std_logic_vector( 31 downto 0) := x"00000001"
Time format 00HHMMSS in decimal.
Definition: top_rod_efex.vhd:61
top_rod_efex.GLOBAL_DATE
GLOBAL_DATE std_logic_vector( 31 downto 0) := x"20200909"
Definition: top_rod_efex.vhd:59
top_rod_efex.TOP_VER
TOP_VER std_logic_vector( 31 downto 0) := x"00000004"
Version of the top folder, see TOP_SHA.
Definition: top_rod_efex.vhd:67
top_rod_efex.CON_SHA
CON_SHA std_logic_vector( 31 downto 0) := x"00000007"
Short 7-digit git SHA of the Hog submodule.
Definition: top_rod_efex.vhd:72
top_rod_efex.HOG_SHA
HOG_SHA std_logic_vector( 31 downto 0) := x"00000009"
Short 7-digit git SHA of the Hog submodule.
Definition: top_rod_efex.vhd:75
top_rod_efex.XML_SHA
XML_SHA std_logic_vector( 31 downto 0) := x"0000000a"
Short 7-digit git SHA of the XMLs.
Definition: top_rod_efex.vhd:79
top_rod_efex.ROD_EFEX_SHA
ROD_EFEX_SHA std_logic_vector( 31 downto 0) := x"0000000c"
SHA of this build.
Definition: top_rod_efex.vhd:84
top_rod_efex.XML_VER
XML_VER std_logic_vector( 31 downto 0) := x"0000000b"
Version of the XMLs.
Definition: top_rod_efex.vhd:81
top_rod_efex.TOP_SHA
TOP_SHA std_logic_vector( 31 downto 0) := x"00000005"
Short 7-digit git SHA of the top folder: list file, xdcs, XMLs, tcl file and this file.
Definition: top_rod_efex.vhd:69
top_rod_efex.GLOBAL_SHA
GLOBAL_SHA std_logic_vector( 31 downto 0) := x"00000003"
Short 7-digit git SHA of the repository.
Definition: top_rod_efex.vhd:65
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1