ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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packet_fifo.vhd
1 
3 ----------------------------------------------------------------------------------
4 -- Company:
5 -- Engineer:
6 --
7 -- Create Date: 05.12.2017 18:10:07
8 -- Design Name:
9 -- Module Name: packet_fifo - RTL
10 -- Project Name:
11 -- Target Devices:
12 -- Tool Versions:
13 -- Description:
14 --
15 -- Dependencies:
16 --
17 -- Revision:
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
20 --
21 ----------------------------------------------------------------------------------
22 
23 
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx leaf cells in this code.
33 --library UNISIM;
34 --use UNISIM.VComponents.all;
35 
36 entity packet_fifo is
37  Port (
38  --Slave (input) side
39  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
40  s_axis_tvalid : IN STD_LOGIC;
41  s_axis_tlast : IN STD_LOGIC;
42  s_axis_tready : OUT STD_LOGIC;
43 
44  --Master (output) side
45  m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46  m_axis_tvalid : OUT STD_LOGIC;
47  m_axis_tready : IN STD_LOGIC;
48  m_axis_tlast : OUT STD_LOGIC;
49 
50  --control
51  -- DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52  WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53  RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54  fifo_full : out std_logic;
55  clk_160 : in std_logic; --this is pp_clock (not necessarily 160MHz)
56  clk_240 : in std_logic;
57  RESET : in std_logic;
58  flx_backpressure : in std_logic;
59  flx_bp_enable : in std_logic;
60  flx_bp_240 : out std_logic --flx_backpressure sync'ed to 240MHz TXUSR clk
61 
62  );
63 end packet_fifo;
64 
65 architecture RTL of packet_fifo is
66 
67 
68 
69 
70 COMPONENT axis_dwidth_64_32
71  PORT (
72  aclk : IN STD_LOGIC;
73  aresetn : IN STD_LOGIC;
74  s_axis_tvalid : IN STD_LOGIC;
75  s_axis_tready : OUT STD_LOGIC;
76  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
77  s_axis_tlast : IN STD_LOGIC;
78  m_axis_tvalid : OUT STD_LOGIC;
79  m_axis_tready : IN STD_LOGIC;
80  m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81  m_axis_tlast : OUT STD_LOGIC
82  );
83 END COMPONENT;
84 
85 COMPONENT axis_data_fifo_0
86  PORT (
87  s_axis_aresetn : IN STD_LOGIC;
88 -- m_axis_aresetn : IN STD_LOGIC;
89  s_axis_aclk : IN STD_LOGIC;
90  s_axis_tvalid : IN STD_LOGIC;
91  s_axis_tready : OUT STD_LOGIC;
92  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
93  s_axis_tlast : IN STD_LOGIC;
94  m_axis_aclk : IN STD_LOGIC;
95  m_axis_tvalid : OUT STD_LOGIC;
96  m_axis_tready : IN STD_LOGIC;
97  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
98  m_axis_tlast : OUT STD_LOGIC;
99 -- axis_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100  axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101  axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102  prog_full : OUT STD_LOGIC
103  );
104 END COMPONENT;
105 
106 COMPONENT ila_fifo
107 
108 PORT (
109  clk : IN STD_LOGIC;
110 
111  probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
112  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
113  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
114  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
115  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
116  probe5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
117  probe6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
118  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
119  probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
121  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
122  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
123  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
124 );
125 END COMPONENT ;
126 
127 signal axis_tdata : STD_LOGIC_VECTOR(63 DOWNTO 0);
128 signal axis_tvalid : std_logic;
129 signal axis_tlast : std_logic;
130 signal axis_tready : std_logic;
131 signal aresetn : std_logic;
132 signal axis_data_count : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 signal axis_wr_data_count : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 signal axis_rd_data_count : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 signal m_axis_tdata_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 signal m_axis_tvalid_i : std_logic;
137 signal m_axis_tlast_i : std_logic;
138 signal s_axis_tready_i : std_logic;
139 
140 signal flx_bp_sync_0 : STD_LOGIC;
141 signal flx_bp_sync_1 : STD_LOGIC;
142 signal m_axis_tvalid_bp : STD_LOGIC;
143 signal m_axis_tready_bp : STD_LOGIC;
144 
145 attribute async_reg : string;
146 attribute async_reg of flx_bp_sync_0 : signal is "true";
147 attribute async_reg of flx_bp_sync_1 : signal is "true";
148 attribute dont_touch : string;
149 attribute dont_touch of flx_bp_sync_0 : signal is "true";
150 attribute dont_touch of flx_bp_sync_1 : signal is "true";
151 
152 
153 
154 begin
155 
156 m_axis_tdata <= m_axis_tdata_i;
157 --m_axis_tvalid <= m_axis_tvalid_i;
158 m_axis_tvalid <= m_axis_tvalid_bp;
159 m_axis_tlast <= m_axis_tlast_i;
160 
161 m_axis_tvalid_bp <= m_axis_tvalid_i and not flx_bp_sync_1;
162 m_axis_tready_bp <= m_axis_tready and not flx_bp_sync_1;
163 
164 
165 data_width_conv : axis_dwidth_64_32
166  PORT MAP (
167  aclk => clk_240,
168  aresetn => aresetn,
169  s_axis_tvalid => axis_tvalid,
170  s_axis_tready => axis_tready,
171  s_axis_tdata => axis_tdata,
172 -- s_axis_tdata(31 downto 0) => axis_tdata(63 downto 32),
173 -- s_axis_tdata(63 downto 32) => axis_tdata(31 downto 0),
174  s_axis_tlast => axis_tlast,
175  m_axis_tvalid => m_axis_tvalid_i,
176  m_axis_tready => m_axis_tready_bp,
177  m_axis_tdata => m_axis_tdata_i,
178  m_axis_tlast => m_axis_tlast_i
179  );
180 
181 main_fifo : axis_data_fifo_0
182  PORT MAP (
183  s_axis_aresetn => aresetn,
184 -- m_axis_aresetn => aresetn,
185  s_axis_aclk => clk_160,
186  s_axis_tvalid => s_axis_tvalid,
187  s_axis_tready => s_axis_tready_i,
188  s_axis_tdata => s_axis_tdata,
189  s_axis_tlast => s_axis_tlast,
190  m_axis_aclk => clk_240,
191  m_axis_tvalid => axis_tvalid,
192  m_axis_tready => axis_tready,
193  m_axis_tdata => axis_tdata,
194  m_axis_tlast => axis_tlast,
195 -- axis_data_count => axis_data_count,
196  axis_wr_data_count => axis_wr_data_count,
197  axis_rd_data_count => axis_rd_data_count,
198  prog_full => fifo_full
199  );
200 
201 ILA_packet_fifo : ila_fifo
202 PORT MAP (
203  clk => clk_240,
204 
205  probe0 => axis_tdata,
206  probe1(0) => axis_tvalid,
207  probe2(0) => axis_tlast,
208  probe3(0) => axis_tready,
209  probe4(0) => flx_bp_sync_1,
210  probe5 => axis_wr_data_count,
211  probe6 => axis_rd_data_count,
212  probe7(0) => aresetn,
213  probe8 => m_axis_tdata_i,
214  probe9(0) => m_axis_tvalid_bp,
215  probe10(0) => m_axis_tlast_i,
216  probe11(0) => s_axis_tready_i,
217  probe12(0) => m_axis_tready_bp
218 );
219 
220 s_axis_tready <= s_axis_tready_i;
221 
222 --DATA_COUNT <= axis_data_count;
223 WR_DATA_COUNT <= axis_wr_data_count;
224 RD_DATA_COUNT <= axis_rd_data_count;
225 
226 aresetn <= not reset;
227 
228 --synchronise the felix backpressure signals to the packet processor clock
229 process (clk_240) begin
230  if (rising_edge(clk_240)) then
231  flx_bp_sync_0 <= (flx_backpressure and flx_bp_enable);
232  flx_bp_sync_1 <= flx_bp_sync_0;
233  end if;
234 end process;
235 
236 flx_bp_240 <= flx_bp_sync_1;
237 
238 end RTL;
packet_fifo.RTL
Definition: packet_fifo.vhd:65
packet_fifo
Definition: packet_fifo.vhd:36
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