RTL Architecture Reference

Processes
PROCESS_3	( clk_240 )

Components
axis_dwidth_64_32
axis_data_fifo_0
ila_fifo

Signals
axis_tdata	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
axis_tvalid	std_logic
axis_tlast	std_logic
axis_tready	std_logic
aresetn	std_logic
axis_data_count	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
axis_wr_data_count	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
axis_rd_data_count	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
m_axis_tdata_i	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
m_axis_tvalid_i	std_logic
m_axis_tlast_i	std_logic
s_axis_tready_i	std_logic
flx_bp_sync_0	STD_LOGIC
flx_bp_sync_1	STD_LOGIC
m_axis_tvalid_bp	STD_LOGIC
m_axis_tready_bp	STD_LOGIC

Attributes
async_reg	string
async_reg	signal is " true "
dont_touch	string
dont_touch	signal is " true "

Instantiations
data_width_conv	axis_dwidth_64_32
main_fifo	axis_data_fifo_0
ila_packet_fifo	ila_fifo

Detailed Description

Definition at line 65 of file packet_fifo.vhd.

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The documentation for this class was generated from the following file:

• ROD/rod_efex/hdl/packet_fifo.vhd