packet_fifo Entity Reference

Inheritance diagram for packet_fifo:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
s_axis_tdata	in	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
s_axis_tvalid	in	STD_LOGIC
s_axis_tlast	in	STD_LOGIC
s_axis_tready	out	STD_LOGIC
m_axis_tdata	out	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
m_axis_tvalid	out	STD_LOGIC
m_axis_tready	in	STD_LOGIC
m_axis_tlast	out	STD_LOGIC
WR_DATA_COUNT	out	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
RD_DATA_COUNT	out	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
fifo_full	out	std_logic
clk_160	in	std_logic
clk_240	in	std_logic
RESET	in	std_logic
flx_backpressure	in	std_logic
flx_bp_enable	in	std_logic
flx_bp_240	out	std_logic

Detailed Description

Definition at line 36 of file packet_fifo.vhd.

Member Data Documentation

IEEE

IEEE

Library

packet_fifo referred to as Output Staging FIFO - Sits between each processor and its full mode output interface Data may accumulate following several consecutive events or during times of Felix backpressure

Definition at line 24 of file packet_fifo.vhd.

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The documentation for this class was generated from the following file:

• ROD/rod_efex/hdl/packet_fifo.vhd