fex_rx_checker.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 01.04.2022 14:17:38
-- Design Name: 
-- Module Name: fex_rx_checker - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity fex_rx_checker is
    Port ( clock        : in STD_LOGIC;
           reset        : in STD_LOGIC; 
           tvalid       : in STD_LOGIC;
           tlast        : in STD_LOGIC;
           tdata        : in STD_logic_vector(63 downto 0); 
           channel_up   : in STD_LOGIC; 
           soft_error   : in STD_LOGIC;
           hard_error   : in STD_LOGIC;
           L1A          : in STD_LOGIC;
           l1id_mis_stretch  : in std_logic
           );
end fex_rx_checker;
 
architecture RTL of fex_rx_checker is
 
component backplane_crc is
  generic (
    fex_check             : integer := 0;
    crc20_G_Poly          : std_logic_vector(19 downto 0) := x"8349f"   --old poly
    );
  Port ( 
  clock         : in    std_logic;
  reset         : in    std_logic;
  s_tvalid      : in    std_logic;
  s_tlast       : in    std_logic;
  s_tdata       : in    std_logic_vector(63 downto 0);
  header_error  : out   std_logic;
  payload_error : out   std_logic;
  length_error  : out   std_logic
  );
end component;
 
COMPONENT chan_crc_ila
 
PORT (
    clk : IN STD_LOGIC;
    probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); 
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT  ;
 
signal  header_crc9_error  : std_logic;
signal  payload_crc20_error : std_logic;
signal  length_error  : std_logic;
signal  L1A_sync_cdc_to : std_logic;
signal  L1A_sync2       : std_logic;
 
ATTRIBUTE async_reg                     : STRING;
ATTRIBUTE async_reg of L1A_sync_cdc_to  : SIGNAL IS "true";
 
begin
 
 
crc_checker : backplane_crc 
 generic map ( 
     fex_check      => 1, 
     crc20_G_Poly   => x"8359f" 
     )
  Port map( 
    clock         =>  clock,
    reset         =>  reset,
    s_tvalid      =>  tvalid,
    s_tlast       =>  tlast,
    s_tdata       =>  tdata,
    header_error  =>  header_crc9_error,
    payload_error =>  payload_crc20_error,
    length_error  =>  length_error
  );
 
 
ila_crc_check  : chan_crc_ila
  port map (
    clk   => clock,
    probe0    => tdata,
    probe1(0) => tvalid, 
    probe2(0) => tlast,
    probe3(0) => channel_up, 
    probe4(0) => header_crc9_error,
    probe5(0) => payload_crc20_error,
    probe6(0) => length_error, 
    probe7(0) => soft_error, 
    probe8(0) => hard_error,
    probe9(0) => L1A_sync2,
    probe10(0) => l1id_mis_stretch
    );
 
 
process (clock) begin
  if rising_edge(clock) then 
     L1A_sync_cdc_to <= L1A;
     L1A_sync2       <= L1A_sync_cdc_to;
   end if; 
end process; 
 
 
 
 
 
end RTL;