backplane_crc.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 22.09.2021 10:58:44
-- Design Name: 
-- Module Name: testbench_crc - rtl
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity backplane_crc is
  generic (
    fex_check             : integer := 0;
    crc20_G_Poly          : std_logic_vector(19 downto 0) := x"8349f"   --old poly
    );
  Port ( 
  clock         : in    std_logic;
  reset         : in    std_logic;
  s_tvalid      : in    std_logic;
  s_tlast       : in    std_logic;
  s_tdata       : in    std_logic_vector(63 downto 0);
  header_error  : out   std_logic;
  payload_error : out   std_logic;
  length_error  : out   std_logic
  );
end backplane_crc;
 
architecture rtl of backplane_crc is
 
--incoming packet types 
constant tob   : std_logic_vector( 1 downto 0) := "01";
constant raw   : std_logic_vector( 1 downto 0) := "10";
constant debug : std_logic_vector( 1 downto 0) := "11";
 
component CRC 
   generic(
     Nbits :  positive  := 64;
     CRC_Width        :  positive   := 20;
 --    G_Poly: Std_Logic_Vector :=x"c1acf";
     G_Poly: Std_Logic_Vector :=x"8349f";
     G_InitVal: std_logic_vector:=x"fffff"
     );
   port(
     CRC   : out    std_logic_vector(CRC_Width-1 downto 0);
     Calc  : in     std_logic;
     Clk   : in     std_logic;
     DIn   : in     std_logic_vector(Nbits-1 downto 0);
     Reset : in     std_logic
     
     );
end component;
 
component osum_crc9d32 
   port(
    clock : in std_logic;
 
    crc_start : in std_logic;
    d_in      : in std_logic_vector(31 downto 0);
 
    crc_out : out std_logic_vector(8 downto 0)
    );
    
end component;
 
 
 
signal CRC20_out    : std_logic_vector(19 downto 0);
signal crc20_calc   : std_logic;
signal crc20_din    : std_logic_vector(63 downto 0);
 
signal CRC9_out    : std_logic_vector(8 downto 0);
signal crc9_calc   : std_logic;
signal crc9_din    :  std_logic_vector(63 downto 0);
signal crc_din_32  :  std_logic_vector(31 downto 0);
signal crc_din_sel : std_logic_vector (2 downto 0);
signal s_tvalid_del  : std_logic;
signal s_tvalid_del2 : std_logic;
 
signal s_tlast_del  : std_logic;
signal s_tlast_del2 : std_logic;
 
signal s_first_cyc  : std_logic;
signal s_second_cyc  : std_logic;
signal s_third_cyc  : std_logic;
signal s_fourth_cyc  : std_logic;
signal in_progress  : std_logic;
signal in_progress_del1  : std_logic;
signal in_progress_del2  : std_logic;
signal proposed_crc9    :  std_logic_vector(8 downto 0);
signal proposed_crc20   :  std_logic_vector(19 downto 0);
signal proposed_length  :  std_logic_vector(15 downto 0); 
signal header_error_i   :  std_logic;
signal payload_error_i  :  std_logic;
 
signal swap_data        :  std_logic_vector(63 downto 0);
signal word2_reg        :  std_logic_vector(31 downto 0);
signal word3_reg        :  std_logic_vector(31 downto 0);
 
signal stream_id        :  std_logic_vector(7 downto 0);
signal pkt_type         :  std_logic_vector(1 downto 0);
signal early_pkt_type   :  std_logic_vector(1 downto 0);
signal crc9_samp        :  std_logic;
 
signal start_crc20_calc :  std_logic;
signal length_counter   :  std_logic_vector(15 downto 0);
signal measured_length  :  std_logic_vector(15 downto 0);
signal length_error_i   :  std_logic;
 
 
signal crc9_out_64       : std_logic_vector(8 downto 0);
signal crc20_reset       : std_logic;
 
begin
 
--pkt_type <= stream_id(7 downto 6);
 
early_pkt_type <= (s_first_cyc and s_tdata(7)) & (s_first_cyc and s_tdata(7));
 
with s_first_cyc select 
  pkt_type <=   early_pkt_type           when '1',
                stream_id(7 downto 6)    when others;
 
with s_first_cyc select 
   crc9_din <= (s_tdata(31 downto 29) & "000000000" & s_tdata(19 downto 0) & s_tdata(63 downto 32)) when '1', 
               (s_tdata (31 downto 0) &  s_tdata(63 downto 32)) when others;
 
with s_tlast select  
   crc20_din <= (s_tdata(31 downto 0) & x"00000" & s_tdata(43 downto 32)) when '1',
                (s_tdata (31 downto 0) &  s_tdata(63 downto 32)) when others;
 
 
 
 
 
payload_crc : CRC
  generic map (
     Nbits     => 64,
     CRC_Width => 20,
 --    G_Poly    => x"c1acf",
     G_Poly    => crc20_G_Poly,
     G_InitVal => x"fffff"
     )
 port map( 
          Clk   =>   Clock,
          CRC    =>  CRC20_out,
          Calc   =>  crc20_Calc,
          Din    =>  crc20_din,
 --         Reset  =>  s_first_cyc
          Reset  =>  crc20_reset
          );
crc20_reset <= s_first_cyc or reset;
 
header_crc : CRC
 generic map (
         Nbits      => 64,
         CRC_Width  => 9,
         G_Poly     => "011111011",   --this one is correct 
         G_InitVal  => "111111111"   
         )
 port map( 
          Clk   =>   Clock,
          CRC    =>  crc9_out_64, --CRC9_out,
          Calc   =>  crc9_Calc,
          Din    =>  crc9_din,  
--          Reset  =>  reset
           Reset  =>  crc20_reset
          );
 
 
three_word_header_crc : osum_crc9d32
   port map( 
          clock     =>  clock,
 
          CRC_out   => crc9_out,
          crc_start =>  s_first_cyc,
          d_in      =>  CRC_din_32
          );
 
crc_din_sel <= s_third_cyc & s_second_cyc & s_first_cyc;
 
with crc_din_sel select 
     CRC_din_32 <= (s_tdata(31 downto 29) & "000000000" & s_tdata(19 downto 0)) when "001",
                    word2_reg                                                   when "010",
                    word3_reg                                                   when others;
                    
                    
 process (clock) begin
   if rising_edge(clock) then 
      if (s_first_cyc = '1') then 
         stream_id <= s_tdata(7 downto 0);
      else 
         stream_id <= stream_id;
      end if;
   end if;   
 end process;
                    
 
process (clock) begin
   if rising_edge(clock) then 
      if (s_first_cyc = '1') then 
         word2_reg <= s_tdata(63 downto 32);
         word3_reg <= word3_reg;
      elsif (s_second_cyc = '1') then 
         word3_reg <= s_tdata(31 downto 0);
         word2_reg <= word2_reg;
      else 
         word2_reg <= word2_reg;
         word3_reg <= word3_reg;
      end if; 
   end if;   
 end process;     
 
 
 
process (clock) begin
   if rising_edge(clock) then 
      if (reset = '1') then 
         s_tvalid_del  <= '0';
         s_tvalid_del2 <= '0'; 
      else
         s_tvalid_del  <= s_tvalid;
         s_tvalid_del2 <= s_tvalid_del; 
      end if;
   end if; 
 end process;
 
process (clock) begin
   if rising_edge(clock) then 
      if (reset = '1') then 
         s_tlast_del  <= '0';
         s_tlast_del2 <= '0'; 
      else
         s_tlast_del  <= s_tlast;
         s_tlast_del2 <= s_tlast_del; 
      end if;
   end if; 
 end process; 
 
 
rod_test_1 : if fex_check = 0 generate
 
with pkt_type select 
  start_crc20_calc <= s_first_cyc when debug,
                      s_second_cyc when others;
 
end generate rod_test_1;
 
fex_test_1 : if fex_check = 1 generate
 start_crc20_calc <= s_first_cyc;
end generate fex_test_1;
 
 
 
--process (clock) begin
--   if rising_edge(clock) then 
--      if (reset = '1') or (s_tlast = '1')then 
--         crc20_calc  <= '0'; 
--      elsif  (start_crc20_calc = '1') then  
--         crc20_calc  <= '1';  
--      end if;
--   end if;     
--end process;       
crc20_calc  <= s_tvalid and in_progress;
 
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_tlast = '1')  then
           in_progress <= '0';
        elsif  (s_first_cyc = '1') and (s_tlast = '0') then  
           in_progress <= '1';
        else 
           in_progress <= in_progress;
        end if;
     end if;    
 end process;
 
 process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') then
           in_progress_del1 <= '0';
           in_progress_del2 <= '0';
        else 
           in_progress_del1 <= in_progress;
           in_progress_del2  <= in_progress_del1;
        end if; 
     end if;   
  end process;             
 
 
------------------prev cycle empty-------------or        previous cycle was tlast       ----
s_first_cyc <= ((s_tvalid and not s_tvalid_del) or (s_tvalid and s_tvalid_del and s_tlast_del)) and not in_progress; 
--s_first_cyc <= ((s_tvalid and not s_tvalid_del) or (s_tvalid and s_tvalid_del and s_tlast_del)); 
--s_first_cyc <= ((s_tvalid and not s_tvalid_del) or (s_tvalid and s_tvalid_del and not s_tlast_del))  and not in_progress;
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_tlast = '1')  then
           s_second_cyc <= '0';
           s_third_cyc <= '0';
           s_fourth_cyc <= '0';
        else
           s_second_cyc <= s_first_cyc; 
           s_third_cyc <= s_second_cyc;
           s_fourth_cyc <= s_third_cyc;   
        end if;
   end if;
end process;   
 
rod_test2: if fex_check = 0 generate 
  crc9_calc <= s_first_cyc or s_second_cyc;
end generate rod_test2;
  
fex_test2: if fex_check = 1 generate 
  crc9_calc <= s_first_cyc;
end generate fex_test2;  
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_tlast = '1')  then
           proposed_crc9 <= "000000000";
        elsif (s_first_cyc = '1') then 
           proposed_crc9 <= s_tdata(28 downto 20); 
        end if; 
  end if;
end process;        
 
       
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') then --or (s_first_cyc = '1')  then
           proposed_crc20 <= x"00000";
           proposed_length <= x"0000";
        elsif (s_tlast = '1') and (s_tvalid = '1')  then 
           proposed_crc20 <= s_tdata(63 downto 44);
           proposed_length <=  s_tdata(15 downto 0);
        end if; 
  end if;
end process;     
 
 
--header error flag
 
rod_test3: if fex_check = 0 generate 
with pkt_type select 
  crc9_samp <= (s_third_cyc and in_progress) when debug,
               (s_fourth_cyc and in_progress) when others;
 
  
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_first_cyc = '1') then   ---make this sticky for the whole sim
           header_error_i <= '0';
        elsif (crc9_samp = '1') and (proposed_crc9 /= crc9_out) then 
            header_error_i <= '1'; 
        else    
            header_error_i <= header_error_i;
        end if;
  end if;
end process;
 
end generate rod_test3;
 
fex_test3: if fex_check = 1 generate 
  crc9_samp <= (s_third_cyc and in_progress);
  
  
 process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_first_cyc = '1') then   ---make this sticky for the whole sim
           header_error_i <= '0';
        elsif (crc9_samp = '1') and (proposed_crc9 /= crc9_out_64) then 
            header_error_i <= '1'; 
        else    
            header_error_i <= header_error_i;
        end if;
  end if;
end process; 
  
 end generate fex_test3;
 
 
 
 
header_error <= header_error_i;
 
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_first_cyc = '1') then   ---make this sticky for the whole sim
           payload_error_i <= '0';
        elsif (s_tlast_del2 = '1') and (in_progress_del2 = '1') and (proposed_crc20 /= crc20_out) then 
           payload_error_i <= '1'; 
        else    
            payload_error_i <= payload_error_i;
        end if;
  end if;
end process;
 
payload_error <= payload_error_i;    
 
---length counter -----
process(clock) begin
  if rising_edge (clock) then
        if (reset = '1') or (s_first_cyc = '1') then 
           length_counter <= x"0000";
        elsif (crc20_Calc = '1') then 
           length_counter <= (length_counter + 2);
        else 
           length_counter <= length_counter;
        end if; 
   end if;
end process;       
 
process(clock) begin
  if rising_edge (clock) then
      if (reset = '1') then 
           measured_length <= x"0000";
      elsif (s_tlast = '1') and (s_tvalid = '1') and (in_progress = '1') then 
           measured_length <= length_counter;
      else  
           measured_length <= measured_length;
         end if; 
   end if;
end process;          
 
 
process(clock) begin
  if rising_edge (clock) then
      if (reset = '1') or (s_first_cyc = '1') then 
           length_error_i <= '0';
      elsif (s_tlast_del = '1') and (measured_length /= proposed_length) then 
           length_error_i <= '1';     
      else 
           length_error_i <= length_error_i;
         end if; 
   end if;
end process;          
           
 length_error <=  length_error_i;
end rtl;