rtl Architecture Reference

Processes
PROCESS_42	( clock )
PROCESS_43	( clock )
PROCESS_44	( clock )
PROCESS_45	( clock )
PROCESS_46	( clock )
PROCESS_47	( clock )
PROCESS_48	( clock )
PROCESS_49	( clock )
PROCESS_50	( clock )
PROCESS_51	( clock )
PROCESS_52	( clock )
PROCESS_53	( clock )
PROCESS_54	( clock )
PROCESS_55	( clock )
PROCESS_56	( clock )

Components
CRC	<Entity CRC>
osum_crc9d32	<Entity osum_crc9d32>

Constants
tob	std_logic_vector ( 1 downto 0 ) := " 01 "
raw	std_logic_vector ( 1 downto 0 ) := " 10 "
debug	std_logic_vector ( 1 downto 0 ) := " 11 "

Signals
CRC20_out	std_logic_vector ( 19 downto 0 )
crc20_calc	std_logic
crc20_din	std_logic_vector ( 63 downto 0 )
CRC9_out	std_logic_vector ( 8 downto 0 )
crc9_calc	std_logic
crc9_din	std_logic_vector ( 63 downto 0 )
crc_din_32	std_logic_vector ( 31 downto 0 )
crc_din_sel	std_logic_vector ( 2 downto 0 )
s_tvalid_del	std_logic
s_tvalid_del2	std_logic
s_tlast_del	std_logic
s_tlast_del2	std_logic
s_first_cyc	std_logic
s_second_cyc	std_logic
s_third_cyc	std_logic
s_fourth_cyc	std_logic
in_progress	std_logic
in_progress_del1	std_logic
in_progress_del2	std_logic
proposed_crc9	std_logic_vector ( 8 downto 0 )
proposed_crc20	std_logic_vector ( 19 downto 0 )
proposed_length	std_logic_vector ( 15 downto 0 )
header_error_i	std_logic
payload_error_i	std_logic
swap_data	std_logic_vector ( 63 downto 0 )
word2_reg	std_logic_vector ( 31 downto 0 )
word3_reg	std_logic_vector ( 31 downto 0 )
stream_id	std_logic_vector ( 7 downto 0 )
pkt_type	std_logic_vector ( 1 downto 0 )
early_pkt_type	std_logic_vector ( 1 downto 0 )
crc9_samp	std_logic
start_crc20_calc	std_logic
length_counter	std_logic_vector ( 15 downto 0 )
measured_length	std_logic_vector ( 15 downto 0 )
length_error_i	std_logic
crc9_out_64	std_logic_vector ( 8 downto 0 )
crc20_reset	std_logic

Instantiations
payload_crc	CRC <Entity CRC>
header_crc	CRC <Entity CRC>
three_word_header_crc	osum_crc9d32 <Entity osum_crc9d32>

Detailed Description

Definition at line 53 of file backplane_crc.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/backplane_crc.vhd