RTL Architecture Reference

Processes
PROCESS_174	( clock )

Components
backplane_crc	<Entity backplane_crc>
chan_crc_ila

Signals
header_crc9_error	std_logic
payload_crc20_error	std_logic
length_error	std_logic
L1A_sync_cdc_to	std_logic
L1A_sync2	std_logic

Attributes
async_reg	STRING
async_reg	signal is " true "

Instantiations
crc_checker	backplane_crc <Entity backplane_crc>
ila_crc_check	chan_crc_ila

Detailed Description

Definition at line 48 of file fex_rx_checker.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/fex_rx_checker.vhd