fex_rx_checker Entity Reference

Inheritance diagram for fex_rx_checker:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
clock	in	STD_LOGIC
reset	in	STD_LOGIC
tvalid	in	STD_LOGIC
tlast	in	STD_LOGIC
tdata	in	STD_logic_vector ( 63 downto 0 )
channel_up	in	STD_LOGIC
soft_error	in	STD_LOGIC
hard_error	in	STD_LOGIC
L1A	in	STD_LOGIC
l1id_mis_stretch	in	std_logic

Detailed Description

Definition at line 34 of file fex_rx_checker.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/fex_rx_checker.vhd