system_top_reset.vhd

 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity system_top_reset is
generic
    (            
            max_count   : std_logic_vector(31 downto 0) := x"0000FFFF"         
    );
  
 
    Port ( clk40            : in STD_LOGIC;
           rod_button       : in STD_LOGIC;
           sys_top_reset    : out STD_LOGIC;
           sys_top_reset_b : out STD_LOGIC);
end system_top_reset;
 
architecture RTL of system_top_reset is
 
 
 
signal reset_reg    : std_logic := '1';
signal count        : std_logic_vector(31 downto 0) := X"0FFFFFFF";
 
begin
 
   process (clk40) begin
      if rising_edge (clk40) then
           if (rod_button = '0') then
                count <= max_count;
                reset_reg <= '1';
            elsif count /= X"00000000" then
                count <= (count - '1');
                reset_reg <='1';
            else
                reset_reg <='0';
           end if;
      end if;
   end process;
 sys_top_reset <= reset_reg;
 sys_top_reset_b <= not reset_reg;
 
 
end RTL;