RTL Architecture Reference

Processes
PROCESS_5	( clk40 )

Signals
reset_reg	std_logic := ' 1 '
count	std_logic_vector ( 31 downto 0 ) := X " 0FFFFFFF "

Detailed Description

Definition at line 22 of file system_top_reset.vhd.

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The documentation for this class was generated from the following file:

• ROD/rod_efex/hdl/system_top_reset.vhd