packet_processor Entity Reference

Inheritance diagram for packet_processor:

Entities
RTL	architecture

Libraries
IEEE
	Top level packet processing block - includes TOB Processor as well as the three Bulk Processors.

Use Clauses
STD_LOGIC_1164
numeric_std
std_logic_unsigned
std_logic_misc
ipbus
ipbus_decode_L1CaloHubRodProcessor

Generics
SIM	integer := 0
jfex	integer := 0
crc20_G_Poly	std_logic_vector ( 19 downto 0 ) := x " 8349f "
tob_0_flx_bp_link	integer := 0
bulk_0_flx_bp_link	integer := 1
bulk_1_flx_bp_link	integer := 2
bulk_2_flx_bp_link	integer := 3
C_S_AXI_DATA_WIDTH	integer := 32
C_S_AXI_ADDR_WIDTH	integer := 9
bp_width	integer := 64
header_width	integer := 64
event_width	integer := 64

Ports
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in_backplane	in	ipb_wbus
ipb_out_backplane	out	ipb_rbus
ipb_in_processor	in	ipb_wbus
ipb_out_processor	out	ipb_rbus
geo_location	in	STD_LOGIC_VECTOR ( 7 downto 0 )
L1A	out	std_logic
L1A_delay_out	out	std_logic
l1id_mis_stretch	out	std_logic
full_mode_stat_tob_0	in	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_0	in	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_1	in	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_2	in	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_tob_0	in	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_0	in	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_1	in	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_2	in	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_tob_0	out	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_0	out	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_1	out	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_2	out	std_logic_vector ( 31 downto 0 )
stage_fifo_level_tob_0	in	std_logic_vector ( 15 downto 0 )
stage_fifo_level_bulk_0	in	std_logic_vector ( 15 downto 0 )
stage_fifo_level_bulk_1	in	std_logic_vector ( 15 downto 0 )
stage_fifo_level_bulk_2	in	std_logic_vector ( 15 downto 0 )
stage_fifo_busy_tob_0	out	STD_LOGIC
stage_fifo_busy_bulk_0	out	STD_LOGIC
stage_fifo_busy_bulk_1	out	STD_LOGIC
stage_fifo_busy_bulk_2	out	STD_LOGIC
stage_fifo_xoff_tob_0	out	STD_LOGIC
stage_fifo_xoff_bulk_0	out	STD_LOGIC
stage_fifo_xoff_bulk_1	out	STD_LOGIC
stage_fifo_xoff_bulk_2	out	STD_LOGIC
stage_fifo_full_tob_0	in	STD_LOGIC
stage_fifo_full_bulk_0	in	STD_LOGIC
stage_fifo_full_bulk_1	in	STD_LOGIC
stage_fifo_full_bulk_2	in	STD_LOGIC
flx_backpressure	out	std_logic_vector ( 11 downto 0 )
flx_backpressure_tob_0	out	STD_LOGIC
flx_backpressure_bulk_0	out	STD_LOGIC
flx_backpressure_bulk_1	out	STD_LOGIC
flx_backpressure_bulk_2	out	STD_LOGIC
pp_clock	in	STD_LOGIC
clk_40	in	STD_LOGIC
clk_160	in	std_logic
rt_clk	in	std_logic
backplane_control	out	std_logic_vector ( 31 downto 0 )
init_clk	in	std_logic
master_reset	in	std_logic
rod_slot	in	std_logic
ck_pll_lock	in	std_logic
CK_INT	in	STD_LOGIC
SMBALERT_B	in	STD_LOGIC
T_WRN_B	in	STD_LOGIC
ro_user_clock	in	STD_LOGIC
ro_controller_reset	in	STD_LOGIC
ro_txcharisk	out	std_logic_vector ( 3 downto 0 )
ro_txdata	out	std_logic_vector ( 31 downto 0 )
ro_status	in	std_logic_vector ( 7 downto 0 )
aurora_user_clock_0	in	STD_LOGIC
aurora_user_clock_1	in	STD_LOGIC
aurora_user_clock_2	in	STD_LOGIC
aurora_user_clock_3	in	STD_LOGIC
aurora_user_clock_4	in	STD_LOGIC
aurora_user_clock_5	in	STD_LOGIC
aurora_user_clock_6	in	STD_LOGIC
aurora_user_clock_7	in	STD_LOGIC
aurora_user_clock_8	in	STD_LOGIC
aurora_user_clock_9	in	STD_LOGIC
aurora_user_clock_10	in	STD_LOGIC
aurora_user_clock_11	in	STD_LOGIC
aurora_user_clock_12	in	STD_LOGIC
aurora_user_clock_13	in	STD_LOGIC
aurora_user_clock_14	in	STD_LOGIC
aurora_user_clock_15	in	STD_LOGIC
aurora_user_clock_16	in	STD_LOGIC
aurora_user_clock_17	in	STD_LOGIC
aurora_user_clock_18	in	STD_LOGIC
aurora_user_clock_19	in	STD_LOGIC
aurora_user_clock_20	in	STD_LOGIC
aurora_user_clock_21	in	STD_LOGIC
aurora_user_clock_22	in	STD_LOGIC
aurora_user_clock_23	in	STD_LOGIC
aurora_chan_stat_0	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_1	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_2	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_3	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_4	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_5	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_6	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_7	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_8	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_9	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_10	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_11	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_12	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_13	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_14	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_15	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_16	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_17	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_18	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_19	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_20	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_21	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_22	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat_23	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_0	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_1	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_2	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_3	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_4	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_5	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_6	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_7	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_8	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_9	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_10	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_11	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_12	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_13	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_14	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_15	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_16	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_17	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_18	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_19	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_20	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_21	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_22	out	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_23	out	STD_LOGIC_VECTOR ( 31 downto 0 )
System_RESET	in	STD_LOGIC
bp_data_0	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_1	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_2	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_3	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_4	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_5	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_6	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_7	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_8	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_9	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_10	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_11	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_12	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_13	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_14	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_15	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_16	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_17	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_18	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_19	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_20	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_21	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_22	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
bp_data_23	in	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
s_axis_tvalid_0	in	std_logic
s_axis_tvalid_1	in	std_logic
s_axis_tvalid_2	in	std_logic
s_axis_tvalid_3	in	std_logic
s_axis_tvalid_4	in	std_logic
s_axis_tvalid_5	in	std_logic
s_axis_tvalid_6	in	std_logic
s_axis_tvalid_7	in	std_logic
s_axis_tvalid_8	in	std_logic
s_axis_tvalid_9	in	std_logic
s_axis_tvalid_10	in	std_logic
s_axis_tvalid_11	in	std_logic
s_axis_tvalid_12	in	std_logic
s_axis_tvalid_13	in	std_logic
s_axis_tvalid_14	in	std_logic
s_axis_tvalid_15	in	std_logic
s_axis_tvalid_16	in	std_logic
s_axis_tvalid_17	in	std_logic
s_axis_tvalid_18	in	std_logic
s_axis_tvalid_19	in	std_logic
s_axis_tvalid_20	in	std_logic
s_axis_tvalid_21	in	std_logic
s_axis_tvalid_22	in	std_logic
s_axis_tvalid_23	in	std_logic
s_axis_tlast_0	in	std_logic
s_axis_tlast_1	in	std_logic
s_axis_tlast_2	in	std_logic
s_axis_tlast_3	in	std_logic
s_axis_tlast_4	in	std_logic
s_axis_tlast_5	in	std_logic
s_axis_tlast_6	in	std_logic
s_axis_tlast_7	in	std_logic
s_axis_tlast_8	in	std_logic
s_axis_tlast_9	in	std_logic
s_axis_tlast_10	in	std_logic
s_axis_tlast_11	in	std_logic
s_axis_tlast_12	in	std_logic
s_axis_tlast_13	in	std_logic
s_axis_tlast_14	in	std_logic
s_axis_tlast_15	in	std_logic
s_axis_tlast_16	in	std_logic
s_axis_tlast_17	in	std_logic
s_axis_tlast_18	in	std_logic
s_axis_tlast_19	in	std_logic
s_axis_tlast_20	in	std_logic
s_axis_tlast_21	in	std_logic
s_axis_tlast_22	in	std_logic
s_axis_tlast_23	in	std_logic
s_axis_tready_0	out	std_logic
s_axis_tready_1	out	std_logic
s_axis_tready_2	out	std_logic
s_axis_tready_3	out	std_logic
s_axis_tready_4	out	std_logic
s_axis_tready_5	out	std_logic
s_axis_tready_6	out	std_logic
s_axis_tready_7	out	std_logic
s_axis_tready_8	out	std_logic
s_axis_tready_9	out	std_logic
s_axis_tready_10	out	std_logic
s_axis_tready_11	out	std_logic
s_axis_tready_12	out	std_logic
s_axis_tready_13	out	std_logic
s_axis_tready_14	out	std_logic
s_axis_tready_15	out	std_logic
s_axis_tready_16	out	std_logic
s_axis_tready_17	out	std_logic
s_axis_tready_18	out	std_logic
s_axis_tready_19	out	std_logic
s_axis_tready_20	out	std_logic
s_axis_tready_21	out	std_logic
s_axis_tready_22	out	std_logic
s_axis_tready_23	out	std_logic
s_axi_ufc_rx_tdata_0	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_1	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_2	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_3	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_4	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_5	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_6	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_7	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_8	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_9	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_10	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_11	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_12	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_13	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_14	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_15	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_16	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_17	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_18	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_19	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_20	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_21	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_22	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tdata_23	in	std_logic_vector ( 63 downto 0 )
s_axi_ufc_rx_tvalid_0	in	std_logic
s_axi_ufc_rx_tvalid_1	in	std_logic
s_axi_ufc_rx_tvalid_2	in	std_logic
s_axi_ufc_rx_tvalid_3	in	std_logic
s_axi_ufc_rx_tvalid_4	in	std_logic
s_axi_ufc_rx_tvalid_5	in	std_logic
s_axi_ufc_rx_tvalid_6	in	std_logic
s_axi_ufc_rx_tvalid_7	in	std_logic
s_axi_ufc_rx_tvalid_8	in	std_logic
s_axi_ufc_rx_tvalid_9	in	std_logic
s_axi_ufc_rx_tvalid_10	in	std_logic
s_axi_ufc_rx_tvalid_11	in	std_logic
s_axi_ufc_rx_tvalid_12	in	std_logic
s_axi_ufc_rx_tvalid_13	in	std_logic
s_axi_ufc_rx_tvalid_14	in	std_logic
s_axi_ufc_rx_tvalid_15	in	std_logic
s_axi_ufc_rx_tvalid_16	in	std_logic
s_axi_ufc_rx_tvalid_17	in	std_logic
s_axi_ufc_rx_tvalid_18	in	std_logic
s_axi_ufc_rx_tvalid_19	in	std_logic
s_axi_ufc_rx_tvalid_20	in	std_logic
s_axi_ufc_rx_tvalid_21	in	std_logic
s_axi_ufc_rx_tvalid_22	in	std_logic
s_axi_ufc_rx_tvalid_23	in	std_logic
s_axi_ufc_rx_tlast_0	in	std_logic
s_axi_ufc_rx_tlast_1	in	std_logic
s_axi_ufc_rx_tlast_2	in	std_logic
s_axi_ufc_rx_tlast_3	in	std_logic
s_axi_ufc_rx_tlast_4	in	std_logic
s_axi_ufc_rx_tlast_5	in	std_logic
s_axi_ufc_rx_tlast_6	in	std_logic
s_axi_ufc_rx_tlast_7	in	std_logic
s_axi_ufc_rx_tlast_8	in	std_logic
s_axi_ufc_rx_tlast_9	in	std_logic
s_axi_ufc_rx_tlast_10	in	std_logic
s_axi_ufc_rx_tlast_11	in	std_logic
s_axi_ufc_rx_tlast_12	in	std_logic
s_axi_ufc_rx_tlast_13	in	std_logic
s_axi_ufc_rx_tlast_14	in	std_logic
s_axi_ufc_rx_tlast_15	in	std_logic
s_axi_ufc_rx_tlast_16	in	std_logic
s_axi_ufc_rx_tlast_17	in	std_logic
s_axi_ufc_rx_tlast_18	in	std_logic
s_axi_ufc_rx_tlast_19	in	std_logic
s_axi_ufc_rx_tlast_20	in	std_logic
s_axi_ufc_rx_tlast_21	in	std_logic
s_axi_ufc_rx_tlast_22	in	std_logic
s_axi_ufc_rx_tlast_23	in	std_logic
multichannel_busy	out	std_logic
combined_busy	in	std_logic
channel_enable_vio	in	std_logic_vector ( 23 downto 0 )
first_chan_vio	in	std_logic_vector ( 4 downto 0 )
last_chan_vio	in	std_logic_vector ( 4 downto 0 )
TTC_ignore_vio	in	std_logic
debug_ctrl_vio	in	std_logic
m_tvalid_0	out	STD_LOGIC
m_tlast_0	out	STD_LOGIC
m_tdata_0	out	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
m_header_marker_0	out	STD_LOGIC
m_tail_marker_0	out	STD_LOGIC
m_tready_0	in	STD_LOGIC
bulk_m_tvalid_0	out	STD_LOGIC
bulk_m_tlast_0	out	STD_LOGIC
bulk_m_tdata_0	out	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_0	out	STD_LOGIC
bulk_m_tail_marker_0	out	STD_LOGIC
bulk_m_tready_0	in	STD_LOGIC
bulk_m_tvalid_1	out	STD_LOGIC
bulk_m_tlast_1	out	STD_LOGIC
bulk_m_tdata_1	out	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_1	out	STD_LOGIC
bulk_m_tail_marker_1	out	STD_LOGIC
bulk_m_tready_1	in	STD_LOGIC
bulk_m_tvalid_2	out	STD_LOGIC
bulk_m_tlast_2	out	STD_LOGIC
bulk_m_tdata_2	out	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_2	out	STD_LOGIC
bulk_m_tail_marker_2	out	STD_LOGIC
bulk_m_tready_2	in	STD_LOGIC
cttc_user_clk	in	std_logic
ttc_status	in	std_logic_vector ( 31 downto 0 )
ttc_reset	out	std_logic
hub_link_reset	out	std_logic
ttc_seq	in	std_logic_vector ( 1 downto 0 )
ttc_word_0	in	std_logic_vector ( 31 downto 0 )
ttc_word_1	in	std_logic_vector ( 31 downto 0 )
ttc_word_2	in	std_logic_vector ( 31 downto 0 )
ttc_word_3	in	std_logic_vector ( 31 downto 0 )
ttc_mux_ctrl	in	std_logic
BP_CTTC_rxdata	in	std_logic_vector ( 31 downto 0 )
FM_CTTC_rxdata	in	std_logic_vector ( 31 downto 0 )
BP_CTTC_rxcharisk	in	std_logic_vector ( 3 downto 0 )
FM_CTTC_rxcharisk	in	std_logic_vector ( 3 downto 0 )
BP_CTTC_MGT_bus	in	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
FM_CTTC_MGT_bus	in	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
BP_CTTC_rxoutclk	in	STD_LOGIC
FM_CTTC_rxoutclk	in	STD_LOGIC

Detailed Description

Definition at line 44 of file packet_processor.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/packet_processor.vhd