RTL Architecture Reference

Components
tob_processor	<Entity tob_processor>
bulk_processor
input_fifos	<Entity input_fifos>
aurora_in_fifo
ttc_info	<Entity ttc_info>
ev_builder	<Entity ev_builder>
dummy_chan_in	<Entity dummy_chan_in>
pkt_proc_vio
ppmux_ila
ro_controller
pulse_stretch	<Entity pulse_stretch>
combined_ttc_no_mgt
BUFGMUX
cttc_crc_test

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
poll_chan_0	std_logic
poll_chan_1	std_logic
poll_chan_2	std_logic
poll_chan_3	std_logic
poll_chan_4	std_logic
poll_chan_5	std_logic
poll_chan_6	std_logic
poll_chan_7	std_logic
poll_chan_8	std_logic
poll_chan_9	std_logic
poll_chan_10	std_logic
poll_chan_11	std_logic
ch_tdata_0	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_0	std_logic
ch_tlast_0	std_logic
ch_tready_0	std_logic
ch_header_mark_0	std_logic
ch_trailer_mark_0	std_logic
ch_tdata_1	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_1	std_logic
ch_tlast_1	std_logic
ch_tready_1	std_logic
ch_header_mark_1	std_logic
ch_trailer_mark_1	std_logic
ch_tdata_2	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_2	std_logic
ch_tlast_2	std_logic
ch_tready_2	std_logic
ch_header_mark_2	std_logic
ch_trailer_mark_2	std_logic
ch_tdata_3	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_3	std_logic
ch_tlast_3	std_logic
ch_tready_3	std_logic
ch_header_mark_3	std_logic
ch_trailer_mark_3	std_logic
ch_tdata_4	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_4	std_logic
ch_tlast_4	std_logic
ch_tready_4	std_logic
ch_header_mark_4	std_logic
ch_trailer_mark_4	std_logic
ch_tdata_5	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_5	std_logic
ch_tlast_5	std_logic
ch_tready_5	std_logic
ch_header_mark_5	std_logic
ch_trailer_mark_5	std_logic
ch_tdata_6	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_6	std_logic
ch_tlast_6	std_logic
ch_tready_6	std_logic
ch_header_mark_6	std_logic
ch_trailer_mark_6	std_logic
ch_tdata_7	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_7	std_logic
ch_tlast_7	std_logic
ch_tready_7	std_logic
ch_header_mark_7	std_logic
ch_trailer_mark_7	std_logic
ch_tdata_8	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_8	std_logic
ch_tlast_8	std_logic
ch_tready_8	std_logic
ch_header_mark_8	std_logic
ch_trailer_mark_8	std_logic
ch_tdata_9	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_9	std_logic
ch_tlast_9	std_logic
ch_tready_9	std_logic
ch_header_mark_9	std_logic
ch_trailer_mark_9	std_logic
ch_tdata_10	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_10	std_logic
ch_tlast_10	std_logic
ch_tready_10	std_logic
ch_header_mark_10	std_logic
ch_trailer_mark_10	std_logic
ch_tdata_11	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_11	std_logic
ch_tlast_11	std_logic
ch_tready_11	std_logic
ch_header_mark_11	std_logic
ch_trailer_mark_11	std_logic
ch_tdata_12	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_12	std_logic
ch_tlast_12	std_logic
ch_tready_12	std_logic
ch_header_mark_12	std_logic
ch_trailer_mark_12	std_logic
ch_tdata_13	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_13	std_logic
ch_tlast_13	std_logic
ch_tready_13	std_logic
ch_header_mark_13	std_logic
ch_trailer_mark_13	std_logic
ch_tdata_14	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_14	std_logic
ch_tlast_14	std_logic
ch_tready_14	std_logic
ch_header_mark_14	std_logic
ch_trailer_mark_14	std_logic
ch_tdata_15	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ch_tvalid_15	std_logic
ch_tlast_15	std_logic
ch_tready_15	std_logic
ch_header_mark_15	std_logic
ch_trailer_mark_15	std_logic
ev_in_tdata	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
ev_in_tvalid	std_logic
ev_in_tlast	std_logic
ev_in_tready	std_logic
ev_in_header_mark	std_logic
ev_in_trailer_mark	std_logic
nxt_chan_0	std_logic
nxt_chan_1	std_logic
nxt_chan_2	std_logic
nxt_chan_3	std_logic
current_chan	STD_LOGIC_VECTOR ( 4 downto 0 )
m_poll_chan_0	std_logic
dum_chin	STD_LOGIC_VECTOR ( 4 downto 0 )
timeout_err	std_logic
master_header	STD_LOGIC_VECTOR ( 63 downto 0 )
header_read_en	STD_LOGIC
header_fifo_valid	STD_LOGIC
header_fifo_empty	STD_LOGIC
L1ID_error	STD_LOGIC
CTTC_CRC_error	STD_LOGIC
header_fifo_full	STD_LOGIC
timeout_threshold	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_continuity_control	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_continuity_status	STD_LOGIC_vector ( 31 downto 0 )
l1id_local_miss	STD_LOGIC_vector ( 31 downto 0 )
l1id_ttc_miss	STD_LOGIC_vector ( 31 downto 0 )
l1id_error_count	STD_LOGIC_vector ( 31 downto 0 )
repeat_counter	STD_LOGIC_vector ( 31 downto 0 )
bulk_master_header	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_header_fifo_empty	STD_LOGIC
bulk_L1ID_error	STD_LOGIC
bulk_CTTC_CRC_error	STD_LOGIC
bulk_header_read_en	STD_LOGIC
bulk_header_fifo_valid	STD_LOGIC
bulk_header_fifo_full	STD_LOGIC
ev_chan_enable	STD_LOGIC
tob_poll_chan_0	STD_LOGIC
tob_m_tvalid_0	STD_LOGIC
tob_m_tlast_0	STD_LOGIC
tob_m_tready_0	STD_LOGIC
tob_header_marker_0	STD_LOGIC
tob_tail_marker_0	STD_LOGIC
hdr_crc_tag_0	std_logic
tob_m_tdata_0	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_0	STD_LOGIC
calo_m_tvalid_0	STD_LOGIC
calo_m_tlast_0	STD_LOGIC
calo_m_axis_tready_0	STD_LOGIC
calo_header_marker_0	STD_LOGIC
calo_tail_marker_0	STD_LOGIC
calo_m_tdata_0	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_1	STD_LOGIC
tob_m_tvalid_1	STD_LOGIC
tob_m_tlast_1	STD_LOGIC
tob_m_tready_1	STD_LOGIC
tob_header_marker_1	STD_LOGIC
tob_tail_marker_1	STD_LOGIC
hdr_crc_tag_1	STD_LOGIC
tob_m_tdata_1	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_1	STD_LOGIC
calo_m_tvalid_1	STD_LOGIC
calo_m_tlast_1	STD_LOGIC
calo_m_axis_tready_1	STD_LOGIC
calo_header_marker_1	STD_LOGIC
calo_tail_marker_1	STD_LOGIC
calo_m_tdata_1	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_2	STD_LOGIC
tob_m_tvalid_2	STD_LOGIC
tob_m_tlast_2	STD_LOGIC
tob_m_tready_2	STD_LOGIC
tob_header_marker_2	STD_LOGIC
tob_tail_marker_2	STD_LOGIC
hdr_crc_tag_2	STD_LOGIC
tob_m_tdata_2	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_2	STD_LOGIC
calo_m_tvalid_2	STD_LOGIC
calo_m_tlast_2	STD_LOGIC
calo_m_axis_tready_2	STD_LOGIC
calo_header_marker_2	STD_LOGIC
calo_tail_marker_2	STD_LOGIC
calo_m_tdata_2	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_3	STD_LOGIC
tob_m_tvalid_3	STD_LOGIC
tob_m_tlast_3	STD_LOGIC
tob_m_tready_3	STD_LOGIC
tob_header_marker_3	STD_LOGIC
tob_tail_marker_3	STD_LOGIC
hdr_crc_tag_3	STD_LOGIC
tob_m_tdata_3	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_3	STD_LOGIC
calo_m_tvalid_3	STD_LOGIC
calo_m_tlast_3	STD_LOGIC
calo_m_axis_tready_3	STD_LOGIC
calo_header_marker_3	STD_LOGIC
calo_tail_marker_3	STD_LOGIC
calo_m_tdata_3	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_4	STD_LOGIC
tob_m_tvalid_4	STD_LOGIC
tob_m_tlast_4	STD_LOGIC
tob_m_tready_4	STD_LOGIC
tob_header_marker_4	STD_LOGIC
tob_tail_marker_4	STD_LOGIC
hdr_crc_tag_4	STD_LOGIC
tob_m_tdata_4	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_4	STD_LOGIC
calo_m_tvalid_4	STD_LOGIC
calo_m_tlast_4	STD_LOGIC
calo_m_axis_tready_4	STD_LOGIC
calo_header_marker_4	STD_LOGIC
calo_tail_marker_4	STD_LOGIC
calo_m_tdata_4	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_5	STD_LOGIC
tob_m_tvalid_5	STD_LOGIC
tob_m_tlast_5	STD_LOGIC
tob_m_tready_5	STD_LOGIC
tob_header_marker_5	STD_LOGIC
tob_tail_marker_5	STD_LOGIC
hdr_crc_tag_5	STD_LOGIC
tob_m_tdata_5	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_5	STD_LOGIC
calo_m_tvalid_5	STD_LOGIC
calo_m_tlast_5	STD_LOGIC
calo_m_axis_tready_5	STD_LOGIC
calo_header_marker_5	STD_LOGIC
calo_tail_marker_5	STD_LOGIC
calo_m_tdata_5	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_6	STD_LOGIC
tob_m_tvalid_6	STD_LOGIC
tob_m_tlast_6	STD_LOGIC
tob_m_tready_6	STD_LOGIC
tob_header_marker_6	STD_LOGIC
tob_tail_marker_6	STD_LOGIC
hdr_crc_tag_6	STD_LOGIC
tob_m_tdata_6	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_6	STD_LOGIC
calo_m_tvalid_6	STD_LOGIC
calo_m_tlast_6	STD_LOGIC
calo_m_axis_tready_6	STD_LOGIC
calo_header_marker_6	STD_LOGIC
calo_tail_marker_6	STD_LOGIC
calo_m_tdata_6	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_7	STD_LOGIC
tob_m_tvalid_7	STD_LOGIC
tob_m_tlast_7	STD_LOGIC
tob_m_tready_7	STD_LOGIC
tob_header_marker_7	STD_LOGIC
tob_tail_marker_7	STD_LOGIC
hdr_crc_tag_7	STD_LOGIC
tob_m_tdata_7	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_7	STD_LOGIC
calo_m_tvalid_7	STD_LOGIC
calo_m_tlast_7	STD_LOGIC
calo_m_axis_tready_7	STD_LOGIC
calo_header_marker_7	STD_LOGIC
calo_tail_marker_7	STD_LOGIC
calo_m_tdata_7	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_8	STD_LOGIC
tob_m_tvalid_8	STD_LOGIC
tob_m_tlast_8	STD_LOGIC
tob_m_tready_8	STD_LOGIC
tob_header_marker_8	STD_LOGIC
tob_tail_marker_8	STD_LOGIC
hdr_crc_tag_8	STD_LOGIC
tob_m_tdata_8	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_8	STD_LOGIC
calo_m_tvalid_8	STD_LOGIC
calo_m_tlast_8	STD_LOGIC
calo_m_axis_tready_8	STD_LOGIC
calo_header_marker_8	STD_LOGIC
calo_tail_marker_8	STD_LOGIC
calo_m_tdata_8	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_9	STD_LOGIC
tob_m_tvalid_9	STD_LOGIC
tob_m_tlast_9	STD_LOGIC
tob_m_tready_9	STD_LOGIC
tob_header_marker_9	STD_LOGIC
tob_tail_marker_9	STD_LOGIC
hdr_crc_tag_9	STD_LOGIC
tob_m_tdata_9	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_9	STD_LOGIC
calo_m_tvalid_9	STD_LOGIC
calo_m_tlast_9	STD_LOGIC
calo_m_axis_tready_9	STD_LOGIC
calo_header_marker_9	STD_LOGIC
calo_tail_marker_9	STD_LOGIC
calo_m_tdata_9	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_10	STD_LOGIC
tob_m_tvalid_10	STD_LOGIC
tob_m_tlast_10	STD_LOGIC
tob_m_tready_10	STD_LOGIC
tob_header_marker_10	STD_LOGIC
tob_tail_marker_10	STD_LOGIC
hdr_crc_tag_10	STD_LOGIC
tob_m_tdata_10	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_10	STD_LOGIC
calo_m_tvalid_10	STD_LOGIC
calo_m_tlast_10	STD_LOGIC
calo_m_axis_tready_10	STD_LOGIC
calo_header_marker_10	STD_LOGIC
calo_tail_marker_10	STD_LOGIC
calo_m_tdata_10	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_11	STD_LOGIC
tob_m_tvalid_11	STD_LOGIC
tob_m_tlast_11	STD_LOGIC
tob_m_tready_11	STD_LOGIC
tob_header_marker_11	STD_LOGIC
tob_tail_marker_11	STD_LOGIC
hdr_crc_tag_11	STD_LOGIC
tob_m_tdata_11	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_11	STD_LOGIC
calo_m_tvalid_11	STD_LOGIC
calo_m_tlast_11	STD_LOGIC
calo_m_axis_tready_11	STD_LOGIC
calo_header_marker_11	STD_LOGIC
calo_tail_marker_11	STD_LOGIC
calo_m_tdata_11	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_12	STD_LOGIC
tob_m_tvalid_12	STD_LOGIC
tob_m_tlast_12	STD_LOGIC
tob_m_tready_12	STD_LOGIC
tob_header_marker_12	STD_LOGIC
tob_tail_marker_12	STD_LOGIC
hdr_crc_tag_12	STD_LOGIC
tob_m_tdata_12	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_12	STD_LOGIC
calo_m_tvalid_12	STD_LOGIC
calo_m_tlast_12	STD_LOGIC
calo_m_axis_tready_12	STD_LOGIC
calo_header_marker_12	STD_LOGIC
calo_tail_marker_12	STD_LOGIC
calo_m_tdata_12	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_13	STD_LOGIC
tob_m_tvalid_13	STD_LOGIC
tob_m_tlast_13	STD_LOGIC
tob_m_tready_13	STD_LOGIC
tob_header_marker_13	STD_LOGIC
tob_tail_marker_13	STD_LOGIC
hdr_crc_tag_13	STD_LOGIC
tob_m_tdata_13	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_13	STD_LOGIC
calo_m_tvalid_13	STD_LOGIC
calo_m_tlast_13	STD_LOGIC
calo_m_axis_tready_13	STD_LOGIC
calo_header_marker_13	STD_LOGIC
calo_tail_marker_13	STD_LOGIC
calo_m_tdata_13	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_14	STD_LOGIC
tob_m_tvalid_14	STD_LOGIC
tob_m_tlast_14	STD_LOGIC
tob_m_tready_14	STD_LOGIC
tob_header_marker_14	STD_LOGIC
tob_tail_marker_14	STD_LOGIC
hdr_crc_tag_14	STD_LOGIC
tob_m_tdata_14	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_14	STD_LOGIC
calo_m_tvalid_14	STD_LOGIC
calo_m_tlast_14	STD_LOGIC
calo_m_axis_tready_14	STD_LOGIC
calo_header_marker_14	STD_LOGIC
calo_tail_marker_14	STD_LOGIC
calo_m_tdata_14	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_15	STD_LOGIC
tob_m_tvalid_15	STD_LOGIC
tob_m_tlast_15	STD_LOGIC
tob_m_tready_15	STD_LOGIC
tob_header_marker_15	STD_LOGIC
tob_tail_marker_15	STD_LOGIC
hdr_crc_tag_15	STD_LOGIC
tob_m_tdata_15	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_15	STD_LOGIC
calo_m_tvalid_15	STD_LOGIC
calo_m_tlast_15	STD_LOGIC
calo_m_axis_tready_15	STD_LOGIC
calo_header_marker_15	STD_LOGIC
calo_tail_marker_15	STD_LOGIC
calo_m_tdata_15	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_16	STD_LOGIC
tob_m_tvalid_16	STD_LOGIC
tob_m_tlast_16	STD_LOGIC
tob_m_tready_16	STD_LOGIC
tob_header_marker_16	STD_LOGIC
tob_tail_marker_16	STD_LOGIC
hdr_crc_tag_16	STD_LOGIC
tob_m_tdata_16	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_16	STD_LOGIC
calo_m_tvalid_16	STD_LOGIC
calo_m_tlast_16	STD_LOGIC
calo_m_axis_tready_16	STD_LOGIC
calo_header_marker_16	STD_LOGIC
calo_tail_marker_16	STD_LOGIC
calo_m_tdata_16	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_17	STD_LOGIC
tob_m_tvalid_17	STD_LOGIC
tob_m_tlast_17	STD_LOGIC
tob_m_tready_17	STD_LOGIC
tob_header_marker_17	STD_LOGIC
tob_tail_marker_17	STD_LOGIC
hdr_crc_tag_17	STD_LOGIC
tob_m_tdata_17	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_17	STD_LOGIC
calo_m_tvalid_17	STD_LOGIC
calo_m_tlast_17	STD_LOGIC
calo_m_axis_tready_17	STD_LOGIC
calo_header_marker_17	STD_LOGIC
calo_tail_marker_17	STD_LOGIC
calo_m_tdata_17	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_18	STD_LOGIC
tob_m_tvalid_18	STD_LOGIC
tob_m_tlast_18	STD_LOGIC
tob_m_tready_18	STD_LOGIC
tob_header_marker_18	STD_LOGIC
tob_tail_marker_18	STD_LOGIC
hdr_crc_tag_18	STD_LOGIC
tob_m_tdata_18	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_18	STD_LOGIC
calo_m_tvalid_18	STD_LOGIC
calo_m_tlast_18	STD_LOGIC
calo_m_axis_tready_18	STD_LOGIC
calo_header_marker_18	STD_LOGIC
calo_tail_marker_18	STD_LOGIC
calo_m_tdata_18	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_19	STD_LOGIC
tob_m_tvalid_19	STD_LOGIC
tob_m_tlast_19	STD_LOGIC
tob_m_tready_19	STD_LOGIC
tob_header_marker_19	STD_LOGIC
tob_tail_marker_19	STD_LOGIC
hdr_crc_tag_19	STD_LOGIC
tob_m_tdata_19	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_19	STD_LOGIC
calo_m_tvalid_19	STD_LOGIC
calo_m_tlast_19	STD_LOGIC
calo_m_axis_tready_19	STD_LOGIC
calo_header_marker_19	STD_LOGIC
calo_tail_marker_19	STD_LOGIC
calo_m_tdata_19	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_20	STD_LOGIC
tob_m_tvalid_20	STD_LOGIC
tob_m_tlast_20	STD_LOGIC
tob_m_tready_20	STD_LOGIC
tob_header_marker_20	STD_LOGIC
tob_tail_marker_20	STD_LOGIC
hdr_crc_tag_20	STD_LOGIC
tob_m_tdata_20	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_20	STD_LOGIC
calo_m_tvalid_20	STD_LOGIC
calo_m_tlast_20	STD_LOGIC
calo_m_axis_tready_20	STD_LOGIC
calo_header_marker_20	STD_LOGIC
calo_tail_marker_20	STD_LOGIC
calo_m_tdata_20	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_21	STD_LOGIC
tob_m_tvalid_21	STD_LOGIC
tob_m_tlast_21	STD_LOGIC
tob_m_tready_21	STD_LOGIC
tob_header_marker_21	STD_LOGIC
tob_tail_marker_21	STD_LOGIC
hdr_crc_tag_21	STD_LOGIC
tob_m_tdata_21	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_21	STD_LOGIC
calo_m_tvalid_21	STD_LOGIC
calo_m_tlast_21	STD_LOGIC
calo_m_axis_tready_21	STD_LOGIC
calo_header_marker_21	STD_LOGIC
calo_tail_marker_21	STD_LOGIC
calo_m_tdata_21	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_22	STD_LOGIC
tob_m_tvalid_22	STD_LOGIC
tob_m_tlast_22	STD_LOGIC
tob_m_tready_22	STD_LOGIC
tob_header_marker_22	STD_LOGIC
tob_tail_marker_22	STD_LOGIC
hdr_crc_tag_22	STD_LOGIC
tob_m_tdata_22	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_22	STD_LOGIC
calo_m_tvalid_22	STD_LOGIC
calo_m_tlast_22	STD_LOGIC
calo_m_axis_tready_22	STD_LOGIC
calo_header_marker_22	STD_LOGIC
calo_tail_marker_22	STD_LOGIC
calo_m_tdata_22	STD_LOGIC_VECTOR ( 63 downto 0 )
tob_poll_chan_23	STD_LOGIC
tob_m_tvalid_23	STD_LOGIC
tob_m_tlast_23	STD_LOGIC
tob_m_tready_23	STD_LOGIC
tob_header_marker_23	STD_LOGIC
tob_tail_marker_23	STD_LOGIC
hdr_crc_tag_23	STD_LOGIC
tob_m_tdata_23	STD_LOGIC_VECTOR ( 63 downto 0 )
calo_poll_chan_23	STD_LOGIC
calo_m_tvalid_23	STD_LOGIC
calo_m_tlast_23	STD_LOGIC
calo_m_axis_tready_23	STD_LOGIC
calo_header_marker_23	STD_LOGIC
calo_tail_marker_23	STD_LOGIC
calo_m_tdata_23	STD_LOGIC_VECTOR ( 63 downto 0 )
s3_reset_0	STD_LOGIC
s4_reset_0	STD_LOGIC
s4_reset_1	STD_LOGIC
s4_reset_2	STD_LOGIC
s4_reset_3	STD_LOGIC
s5_reset_0	STD_LOGIC
s5_reset_1	STD_LOGIC
s5_reset_2	STD_LOGIC
s5_reset_3	STD_LOGIC
s6_reset_0	STD_LOGIC
s7_reset_0	STD_LOGIC
s8_reset_0	STD_LOGIC
s8_reset_1	STD_LOGIC
s8_reset_2	STD_LOGIC
s8_reset_3	STD_LOGIC
s9_reset_0	STD_LOGIC
s9_reset_1	STD_LOGIC
s9_reset_2	STD_LOGIC
s9_reset_3	STD_LOGIC
s10_reset_0	STD_LOGIC
s11_reset_0	STD_LOGIC
s12_reset_0	STD_LOGIC
s12_reset_1	STD_LOGIC
s12_reset_2	STD_LOGIC
s12_reset_3	STD_LOGIC
s13_reset_0	STD_LOGIC
s13_reset_1	STD_LOGIC
s13_reset_2	STD_LOGIC
s13_reset_3	STD_LOGIC
s14_reset_0	STD_LOGIC
aurora_chan_control_0_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_1_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_2_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_3_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_4_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_5_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_6_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_7_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_8_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_9_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_10_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_11_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_12_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_13_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_14_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_15_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_16_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_17_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_18_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_19_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_20_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_21_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_22_i	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_control_23_i	STD_LOGIC_VECTOR ( 31 downto 0 )
s3_chan_up_0	STD_LOGIC
s4_chan_up_0	STD_LOGIC
s5_chan_up_0	STD_LOGIC
s6_chan_up_0	STD_LOGIC
s7_chan_up_0	STD_LOGIC
s8_chan_up_0	STD_LOGIC
s9_chan_up_0	STD_LOGIC
s10_chan_up_0	STD_LOGIC
s11_chan_up_0	STD_LOGIC
s12_chan_up_0	STD_LOGIC
s13_chan_up_0	STD_LOGIC
s14_chan_up_0	STD_LOGIC
s4_chan_up_1	STD_LOGIC
s4_chan_up_2	STD_LOGIC
s4_chan_up_3	STD_LOGIC
s5_chan_up_1	STD_LOGIC
s5_chan_up_2	STD_LOGIC
s5_chan_up_3	STD_LOGIC
s8_chan_up_1	STD_LOGIC
s8_chan_up_2	STD_LOGIC
s8_chan_up_3	STD_LOGIC
s9_chan_up_1	STD_LOGIC
s9_chan_up_2	STD_LOGIC
s9_chan_up_3	STD_LOGIC
s12_chan_up_1	STD_LOGIC
s12_chan_up_2	STD_LOGIC
s12_chan_up_3	STD_LOGIC
s13_chan_up_1	STD_LOGIC
s13_chan_up_2	STD_LOGIC
s13_chan_up_3	STD_LOGIC
backplane_control_i	STD_LOGIC_VECTOR ( 31 downto 0 )
ttc_fifo_level	STD_LOGIC_VECTOR ( 15 downto 0 )
ttc_reg	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
channel_enable	STD_LOGIC_VECTOR ( 23 downto 0 )
first_chan	STD_LOGIC_vector ( 4 downto 0 )
last_chan	STD_LOGIC_vector ( 4 downto 0 )
channel_enable_reg	STD_LOGIC_VECTOR ( 23 downto 0 )
first_chan_reg	STD_LOGIC_vector ( 4 downto 0 )
last_chan_reg	STD_LOGIC_vector ( 4 downto 0 )
TTC_fifo_rst	std_logic
ttc_ignore	std_logic
ttc_ignore_i	std_logic
TTC_CRC_ignore	std_logic
flx_backpressure_i	STD_LOGIC_VECTOR ( 11 DOWNTO 0 )
link_enable_stat	STD_LOGIC_vector ( 11 downto 0 )
bulk_last_chan	STD_LOGIC_vector ( 4 downto 0 )
header_sequence	STD_LOGIC_VECTOR ( 11 downto 0 )
header_type	STD_LOGIC_VECTOR ( 3 downto 0 )
header_read_en_0	STD_LOGIC
header_read_en_1	STD_LOGIC
header_read_en_2	STD_LOGIC
det_spec_evnt_sel	STD_LOGIC_VECTOR ( 3 downto 0 )
tob_xoff	STD_LOGIC_VECTOR ( 23 downto 0 )
bulk_xoff	STD_LOGIC_VECTOR ( 23 downto 0 )
event_sel	STD_LOGIC_VECTOR ( 1 downto 0 )
L1A_i	STD_LOGIC
event_count	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
orbit_count	STD_LOGIC_VECTOR ( 15 DOWNTO 0 )
event_count_reset	std_logic
orbit_count_reset	std_logic
bcn_adjustment	std_logic_vector ( 11 downto 0 )
reset	std_logic
bkpln_ctrl_reset	std_logic
wdog_fifo_reset	STD_LOGIC
mux_rxusrclk	STD_LOGIC
mux_rx_fsm_reset_done	STD_LOGIC
mux_cpllfbclklost	STD_LOGIC
mux_cplllock	STD_LOGIC
mux_rxbyteisaligned	STD_LOGIC
mux_rxbyterealign	STD_LOGIC
mux_rxchariscomma	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
mux_rxcharisk	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
mux_rxcommadet	STD_LOGIC
mux_rxdata	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
mux_rxdisperr	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
mux_rxnotintable	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
mux_rxresetdone	STD_LOGIC
mux_DRP_CLK_IN	STD_LOGIC
alt_TRACK_DATA_OUT	STD_LOGIC
alt_ttc_word_0	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
alt_ttc_word_1	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
alt_ttc_word_2	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
alt_ttc_word_3	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
alt_ttc_seq	STD_LOGIC_VECTOR ( 1 DOWNTO 0 )
alt_ttc_status	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
alt_ttc_reset	STD_LOGIC
alt_stop_ttc_info	STD_LOGIC
BP_rxoutclk	STD_LOGIC
FM_rxoutclk	STD_LOGIC
mux_CTTC_MGT_bus	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
BP_rxchariscomma	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
BP_rxdisperr	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
BP_rxnotintable	STD_LOGIC
BP_rx_fsm_reset_done	STD_LOGIC
BP_cpllfbclklost	STD_LOGIC
BP_cplllock	STD_LOGIC
BP_rxbyteisaligned	STD_LOGIC
BP_rxbyterealign	STD_LOGIC
BP_rxcommadet	STD_LOGIC
BP_rxresetdone	STD_LOGIC

Instantiations
bkpln_rst_pulse_stretcher	pulse_stretch <Entity pulse_stretch>
fabric	ipbus_fabric_sel
fifo_layer	input_fifos <Entity input_fifos>
tob_processor_0	tob_processor <Entity tob_processor>
ttc_input	ttc_info <Entity ttc_info>
chan_in_gen	dummy_chan_in <Entity dummy_chan_in>
bulk_0	bulk_processor
bulk_1	bulk_processor
bulk_2	bulk_processor
readout_controller	ro_controller
cttc_receiver	combined_ttc_no_mgt
usr_clk_mux_inst	bufgmux
alt_cttc_crc	cttc_crc_test

Detailed Description

Definition at line 500 of file packet_processor.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/packet_processor.vhd