watermark.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.10.2019 10:08:37
-- Design Name: 
-- Module Name: watermark - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity watermark is
         generic (
            watermark_width  : integer :=   4       
         );  
    Port ( 
           clock : in STD_LOGIC;
           level : in STD_LOGIC_VECTOR (watermark_width-1 downto 0);
           reset : in STD_LOGIC;
           watermark: out STD_LOGIC_VECTOR (watermark_width-1 downto 0)
           
           );      
           
end watermark;
 
architecture RTL of watermark is
 
signal   watermark_i : STD_LOGIC_VECTOR (watermark_width-1 downto 0);
 
begin
 
process(clock, reset)
    begin
        if reset = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
            watermark_i <= (others => '0');
        elsif rising_edge(clock) then
            if (level > watermark_i)  then 
              watermark_i <= level;
            else 
               watermark_i <= watermark_i; 
            end if; 
        end if; 
 end process;
 
watermark  <= watermark_i;
 
end RTL;