13 use IEEE.STD_LOGIC_1164.
all;
14 use IEEE.NUMERIC_STD.
all;
21 generic (stage : integer := 4;
27 IN_Words : in DataWordsWithCarry((2**stage)-1 downto 0);
29 OUT_Word : out DataWordWithCarry
35 signal connector : DataWords((2**(stage+1))-2 downto 0);
36 signal carry : std_logic_vector((2**(stage+1))-2 downto 0);
37 signal DelayedOut : DataWords(delay downto 0) := (others => (others => '0'));
38 signal DelayedOverflow : std_logic_vector(delay downto 0) := (others => '0');
42 stage_gen : for s in 0 to (stage - 1) generate
43 adder_gen : for i in 0 to ((2**s) - 1) generate
44 ADD :
entity work.
Adder port map (
46 IN_Carry => carry
(2*(2**s + i
) downto 2*(2**s + i
) -
1),
47 OUT_Carry => carry
((2**s
) -
1 + i
),
48 IN_Words => connector
(2*(2**s + i
) downto 2*(2**s + i
) -
1),
49 OUT_Word => connector
((2**s
) -
1 + i
)
51 end generate adder_gen;
52 end generate stage_gen;
54 input_gen : for i in 0 to ((2**stage) - 1) generate
57 connector((2**stage) - 1 + i) <= IN_Words(i)(DATA_WIDTH - 1 downto 0);
58 carry((2**stage) - 1 + i) <= IN_Words(i)(DATA_WIDTH);
59 end generate input_gen;
61 DelayedOut(DelayedOut'high) <= connector(0);
62 DelayedOverflow(DelayedOverflow'high) <= carry(0);
63 dalay_proc :
process (
CLK)
65 if rising_edge(CLK) then
66 DelayedOverflow(DelayedOverflow'high-1 downto 0) <= DelayedOverflow(DelayedOverflow'high downto 1);
67 DelayedOut(DelayedOut'high-1 downto 0) <= DelayedOut(DelayedOut'high downto 1);
72 OUT_Word(DATA_WIDTH - 1 downto 0) <= DelayedOut(0);
73 OUT_Word(DATA_WIDTH) <= DelayedOverflow(0);
Multiple Adder with carry: adds many input words in cascade, with carry.
Multiple Adder with carry: adds many input words in cascade, with carry.
in CLK std_logic
200 MHz clock