eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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MultiAdderWithCarry.vhd
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1 
11 
12 library IEEE;
13 use IEEE.STD_LOGIC_1164.all;
14 use IEEE.NUMERIC_STD.all;
15 
16 library work;
17 use work.DataTypes.all;
18 
21  generic (stage : integer := 4;
22  delay : integer := 0
23  );
24 
25  port (
26  CLK : in std_logic;
27  IN_Words : in DataWordsWithCarry((2**stage)-1 downto 0);
28 -- OUT_Overflow : out std_logic;
29  OUT_Word : out DataWordWithCarry
30  );
32 
34 architecture Behavioral of MultiAdderWithCarry is
35  signal connector : DataWords((2**(stage+1))-2 downto 0);
36  signal carry : std_logic_vector((2**(stage+1))-2 downto 0);
37  signal DelayedOut : DataWords(delay downto 0) := (others => (others => '0'));
38  signal DelayedOverflow : std_logic_vector(delay downto 0) := (others => '0');
39 
40 begin
41 
42  stage_gen : for s in 0 to (stage - 1) generate
43  adder_gen : for i in 0 to ((2**s) - 1) generate
44  ADD : entity work.Adder port map (
45  CLK => CLK,
46  IN_Carry => carry(2*(2**s + i) downto 2*(2**s + i) - 1),
47  OUT_Carry => carry((2**s) - 1 + i),
48  IN_Words => connector(2*(2**s + i) downto 2*(2**s + i) - 1),
49  OUT_Word => connector((2**s) - 1 + i)
50  );
51  end generate adder_gen;
52  end generate stage_gen;
53 
54  input_gen : for i in 0 to ((2**stage) - 1) generate
55 -- connector((2**(stage+1) - 2) downto ((2**stage) - 1)) <= IN_Words;
56 -- carry((2**(stage+1) - 2) downto ((2**stage) - 1)) <= (others => '0');
57  connector((2**stage) - 1 + i) <= IN_Words(i)(DATA_WIDTH - 1 downto 0);
58  carry((2**stage) - 1 + i) <= IN_Words(i)(DATA_WIDTH);
59  end generate input_gen;
60 
61  DelayedOut(DelayedOut'high) <= connector(0);
62  DelayedOverflow(DelayedOverflow'high) <= carry(0);
63  dalay_proc : process (CLK)
64  begin
65  if rising_edge(CLK) then
66  DelayedOverflow(DelayedOverflow'high-1 downto 0) <= DelayedOverflow(DelayedOverflow'high downto 1);
67  DelayedOut(DelayedOut'high-1 downto 0) <= DelayedOut(DelayedOut'high downto 1);
68  end if;
69 
70  end process;
71 
72  OUT_Word(DATA_WIDTH - 1 downto 0) <= DelayedOut(0);
73  OUT_Word(DATA_WIDTH) <= DelayedOverflow(0);
74 
75 end Behavioral;
2-word adder
Definition: Adder.vhd:14
Multiple Adder with carry: adds many input words in cascade, with carry.
Multiple Adder with carry: adds many input words in cascade, with carry.
in CLK std_logic
200 MHz clock