TauSeedFinder.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
library work;
use work.DataTypes.all;
 
entity TauSeedFinder is
  port (
    CLK            : in  std_logic;
    IN_Central     : in  DataWord;
    IN_Central_of  : in  std_logic;
    
    IN_Surrounding    : in  DataWords(7 downto 0);
    IN_Surrounding_of : in  std_logic_vector(7 downto 0);
    OUT_IsMax         : out std_logic);
end TauSeedFinder;
 
architecture Behavioral of TauSeedFinder is
 
signal half1, half2:  std_logic;
begin
 
  process (CLK)
  variable central       : std_logic_vector(IN_Central'high downto 0);
  variable surrounding0  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding1  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding2  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding3  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding4  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding5  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding6  : std_logic_vector(IN_Central'high  downto 0);
  variable surrounding7  : std_logic_vector(IN_Central'high  downto 0);
  
  begin
    if rising_edge(CLK) then
    central      := (others => '1') when IN_Central_of        = '1' else  IN_Central;
    surrounding0 := (others => '1') when IN_Surrounding_of(0) = '1' else  IN_Surrounding(0);
    surrounding1 := (others => '1') when IN_Surrounding_of(1) = '1' else  IN_Surrounding(1);
    surrounding2 := (others => '1') when IN_Surrounding_of(2) = '1' else  IN_Surrounding(2); 
    surrounding3 := (others => '1') when IN_Surrounding_of(3) = '1' else  IN_Surrounding(3); 
    surrounding4 := (others => '1') when IN_Surrounding_of(4) = '1' else  IN_Surrounding(4); 
    surrounding5 := (others => '1') when IN_Surrounding_of(5) = '1' else  IN_Surrounding(5); 
    surrounding6 := (others => '1') when IN_Surrounding_of(6) = '1' else  IN_Surrounding(6); 
    surrounding7 := (others => '1') when IN_Surrounding_of(7) = '1' else  IN_Surrounding(7); 
    
    -- first clock cycle                  
    -- Up and right: strictly greater than
    
      half1 <= '1' when central > surrounding2 and central > surrounding3 and central > surrounding4 and central > surrounding5 else '0';
 
      -- Down and left: not smaller than
      half2 <= '0' when central < surrounding0 or central < surrounding1 or central < surrounding6 or central < surrounding7 else '1';
 
      --second clock cycle
      OUT_IsMax <= half1 and half2;
    end if;
  end process;
end Behavioral;