AdderTree Entity Reference

Inheritance diagram for AdderTree:

Entities
Behavioral	architecture

Libraries
IEEE
work

Use Clauses
STD_LOGIC_1164
DataTypes	Package <DataTypes>

Ports
CLK	in	std_logic
IN_Words	in	DataWords ( 98 downto 0 )
OUT_Words	out	DataWords ( 21 downto 0 )
OUT_Overflows	out	std_logic_vector ( 21 downto 0 )

Detailed Description

Definition at line 182 of file AdderTree.vhd.

Member Data Documentation

IEEE

IEEE

Library

!!!!!!!!!!!!!!!!! AUTO-GENERATED FILE. PLEASE DO NOT MODIFY !!!!!!!!!!!!!!!!! Generated by graph_vhdl (https://gitlab.cern.ch/taul1ml/graph_vhdl), authored by David Reikher

INPUTS: IN_Words(0) <----— sc0
IN_Words(1) <----— sc1
IN_Words(2) <----— sc2
IN_Words(3) <----— sc3
IN_Words(4) <----— sc4
IN_Words(5) <----— sc5
IN_Words(6) <----— sc6
IN_Words(7) <----— sc7
IN_Words(8) <----— sc8
IN_Words(9) <----— sc9
IN_Words(10) <----— sc10
IN_Words(11) <----— sc11
IN_Words(12) <----— sc12
IN_Words(13) <----— sc13
IN_Words(14) <----— sc14
IN_Words(15) <----— sc15
IN_Words(16) <----— sc16
IN_Words(17) <----— sc17
IN_Words(18) <----— sc18
IN_Words(19) <----— sc19
IN_Words(20) <----— sc20
IN_Words(21) <----— sc21
IN_Words(22) <----— sc22
IN_Words(23) <----— sc23
IN_Words(24) <----— sc24
IN_Words(25) <----— sc25
IN_Words(26) <----— sc26
IN_Words(27) <----— sc27
IN_Words(28) <----— sc28
IN_Words(29) <----— sc29
IN_Words(30) <----— sc30
IN_Words(31) <----— sc31
IN_Words(32) <----— sc32
IN_Words(33) <----— sc33
IN_Words(34) <----— sc34
IN_Words(35) <----— sc35
IN_Words(36) <----— sc36
IN_Words(37) <----— sc37
IN_Words(38) <----— sc38
IN_Words(39) <----— sc39
IN_Words(40) <----— sc40
IN_Words(41) <----— sc41
IN_Words(42) <----— sc42
IN_Words(43) <----— sc43
IN_Words(44) <----— sc44
IN_Words(45) <----— sc45
IN_Words(46) <----— sc46
IN_Words(47) <----— sc47
IN_Words(48) <----— sc48
IN_Words(49) <----— sc49
IN_Words(50) <----— sc50
IN_Words(51) <----— sc51
IN_Words(52) <----— sc52
IN_Words(53) <----— sc53
IN_Words(54) <----— sc54
IN_Words(55) <----— sc55
IN_Words(56) <----— sc56
IN_Words(57) <----— sc57
IN_Words(58) <----— sc58
IN_Words(59) <----— sc59
IN_Words(60) <----— sc60
IN_Words(61) <----— sc61
IN_Words(62) <----— sc62
IN_Words(63) <----— sc63
IN_Words(64) <----— sc64
IN_Words(65) <----— sc65
IN_Words(66) <----— sc66
IN_Words(67) <----— sc67
IN_Words(68) <----— sc68
IN_Words(69) <----— sc69
IN_Words(70) <----— sc70
IN_Words(71) <----— sc71
IN_Words(72) <----— sc72
IN_Words(73) <----— sc73
IN_Words(74) <----— sc74
IN_Words(75) <----— sc75
IN_Words(76) <----— sc76
IN_Words(77) <----— sc77
IN_Words(78) <----— sc78
IN_Words(79) <----— sc79
IN_Words(80) <----— sc80
IN_Words(81) <----— sc81
IN_Words(82) <----— sc82
IN_Words(83) <----— sc83
IN_Words(84) <----— sc84
IN_Words(85) <----— sc85
IN_Words(86) <----— sc86
IN_Words(87) <----— sc87
IN_Words(88) <----— sc88
IN_Words(89) <----— sc89
IN_Words(90) <----— sc90
IN_Words(91) <----— sc91
IN_Words(92) <----— sc92
IN_Words(93) <----— sc93
IN_Words(94) <----— sc94
IN_Words(95) <----— sc95
IN_Words(96) <----— sc96
IN_Words(97) <----— sc97
IN_Words(98) <----— sc98
OUTPUTS: OUT_Words(0) ----—> l2_d1051
OUT_Words(1) ----—> l2_d0375
OUT_Words(2) ----—> l2_d0625
OUT_Words(3) ----—> l0_d0000
OUT_Words(4) ----—> l2_d0125
OUT_Words(5) ----—> l2_d0990
OUT_Words(6) ----—> l1_d1493
OUT_Words(7) ----—> l1_d1315
OUT_Words(8) ----—> l1_d1164
OUT_Words(9) ----—> l1_d1690
OUT_Words(10) ----—> T0
OUT_Words(11) ----—> T1
OUT_Words(12) ----—> T2
OUT_Words(13) ----—> T3
OUT_Words(14) ----—> CORE
OUT_Words(15) ----—> T5
OUT_Words(16) ----—> T6
OUT_Words(17) ----—> T7
OUT_Words(18) ----—> T8
OUT_Words(19) ----—> ET
OUT_Words(20) ----—> EM_ET
OUT_Words(21) ----—> HAD_ET

This adder tree implements the following sums: l2_d1051 = sc49 + sc52 + sc73 + sc76 l2_d0375 = sc61 + sc64 l2_d0625 = sc60 + sc65 l0_d0000 = sc4 l2_d0125 = sc62 + sc63 l2_d0990 = sc50 + sc51 + sc74 + sc75 l1_d1493 = sc10 + sc19 + sc34 + sc43 l1_d1315 = sc11 + sc18 + sc35 + sc42 l1_d1164 = sc12 + sc17 + sc36 + sc41 l1_d1690 = sc9 + sc20 + sc33 + sc44 T0 = sc0 + sc9 + sc10 + sc11 + sc12 + sc45 + sc46 + sc47 + sc48 + sc81 + sc90 T1 = sc1 + sc13 + sc14 + sc15 + sc16 + sc49 + sc50 + sc51 + sc52 + sc82 + sc91 T2 = sc2 + sc17 + sc18 + sc19 + sc20 + sc53 + sc54 + sc55 + sc56 + sc83 + sc92 T3 = sc3 + sc21 + sc22 + sc23 + sc24 + sc57 + sc58 + sc59 + sc60 + sc84 + sc93 CORE = sc4 + sc25 + sc26 + sc27 + sc28 + sc61 + sc62 + sc63 + sc64 + sc85 + sc94 T5 = sc5 + sc29 + sc30 + sc31 + sc32 + sc65 + sc66 + sc67 + sc68 + sc86 + sc95 T6 = sc6 + sc33 + sc34 + sc35 + sc36 + sc69 + sc70 + sc71 + sc72 + sc87 + sc96 T7 = sc7 + sc37 + sc38 + sc39 + sc40 + sc73 + sc74 + sc75 + sc76 + sc88 + sc97 T8 = sc8 + sc41 + sc42 + sc43 + sc44 + sc77 + sc78 + sc79 + sc80 + sc89 + sc98 ET = sc4 + sc25 + sc26 + sc27 + sc28 + sc49 + sc50 + sc51 + sc52 + sc58 + sc59 + sc60 + sc61 + sc62 + sc63 + sc64 + sc65 + sc66 + sc67 + sc73 + sc74 + sc75 + sc76 + sc85 + sc91 + sc93 + sc94 + sc95 + sc97 EM_ET = sc25 + sc26 + sc27 + sc28 + sc49 + sc50 + sc51 + sc52 + sc60 + sc61 + sc62 + sc63 + sc64 + sc65 + sc73 + sc74 + sc75 + sc76 HAD_ET = sc91 + sc93 + sc94 + sc95 + sc97

Outputs are ready at clock cycles marked by 'X': | 0 | 1 | 2 | 3 | 4 | 5 | l2_d1051 | | | | | X | | l2_d0375 | | | | | X | | l2_d0625 | | | | | X | | l0_d0000 | | | | | X | | l2_d0125 | | | | | X | | l2_d0990 | | | | | X | | l1_d1493 | | | | | X | | l1_d1315 | | | | | X | | l1_d1164 | | | | | X | | l1_d1690 | | | | | X | | T0 | | | | | X | | T1 | | | | | X | | T2 | | | | | X | | T3 | | | | | X | | CORE | | | | | X | | T5 | | | | | X | | T6 | | | | | X | | T7 | | | | | X | | T8 | | | | | X | | ET | | | | | | X | EM_ET | | | | | | X | HAD_ET | | | | X | | |

Definition at line 177 of file AdderTree.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/TauBDT/AdderTree.vhd