BDTModel_sparsemux_9_2_6_1_1 Entity Reference

Inheritance diagram for BDTModel_sparsemux_9_2_6_1_1:

Entities
behav	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
numeric_std

Generics
din0_WIDTH	INTEGER := 1
din1_WIDTH	INTEGER := 1
din2_WIDTH	INTEGER := 1
din3_WIDTH	INTEGER := 1
def_WIDTH	INTEGER := 1
sel_WIDTH	INTEGER := 1
dout_WIDTH	INTEGER := 1
CASE0	std_logic_vector ( 1 downto 0 )
CASE1	std_logic_vector ( 1 downto 0 )
CASE2	std_logic_vector ( 1 downto 0 )
CASE3	std_logic_vector ( 1 downto 0 )
ID	INTEGER := 1
NUM_STAGE	INTEGER := 1

Ports
din0	in	std_logic_vector ( din0_WIDTH- 1 downto 0 )
din1	in	std_logic_vector ( din1_WIDTH- 1 downto 0 )
din2	in	std_logic_vector ( din2_WIDTH- 1 downto 0 )
din3	in	std_logic_vector ( din3_WIDTH- 1 downto 0 )
def	in	std_logic_vector ( def_WIDTH- 1 downto 0 )
sel	in	std_logic_vector ( 1 downto 0 )
dout	out	std_logic_vector ( dout_WIDTH- 1 downto 0 )

Detailed Description

Definition at line 12 of file BDTModel_sparsemux_9_2_6_1_1.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1.vhd