EfexDataFormats Package Reference

eFEX data-types and functions More...

Package Body >> EfexDataFormats

Functions
Algoinput	AlgoTowerBuilder ( EmDataIn: in FibreAllEm HadDataIn: in FibreAllHad SpareDataIn: in FibreAllSpare eFEXPosition: in std_logic_vector( 31 downto 0) )
SuperCells	MGT_to_SuperCells ( MGT: in std_logic_vector( 227 downto 0) )
RAW_data_227_type	to_raw_data ( em: in FibreAllEm , had: in FibreAllHad )
std_logic_vector	ReadoutMGTEnable ( fpga_number: in integer , mgt_enable_in: in std_logic_vector( 63 downto 0) )
std_logic_vector	f_efex_position ( fpga_number: in integer , efex_position: in integer )

Procedures
	FibreArrayBuilder( signal fpga_number: in integer signal MGT_DATA: in mgt_data_out signal EmData: out FibreAllEm signal HadData: out FibreAllHad signal SpareData: out FibreAllSpare )

Libraries
IEEE
algolib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
AlgoDataTypes	Package <AlgoDataTypes>
DataTypes	Package <DataTypes>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Constants
EN_EG1	enable_em_chan_type := ( 34 , 32 , 36 , 30 , 37 , 24 , 39 , 22 , 26 , 28 , 31 , 27 , 38 , 29 , 35 , 23 , 33 , 25 , 20 , 21 , 14 , 13 , 15 , 11 , 17 , 12 , 19 , 10 , 18 , 16 , 05 , 01 , 06 , 02 , 08 , 04 , 07 , 00 , 09 , 03 )
EN_HAD1	enable_had_chan_type := ( 55 , 56 , 54 , 59 , 57 , 58 , 42 , 43 , 40 , 48 , 41 , 51 , 44 , 46 , 45 , 50 , 47 , 49 )
EN_SPR1	enable_spare_chan_type := ( 52 , 53 , 60 , 61 , 62 , 63 )
EN_EG2	enable_em_chan_type := ( 34 , 36 , 30 , 35 , 31 , 38 , 33 , 39 , 32 , 37 , 29 , 28 , 26 , 27 , 23 , 25 , 21 , 24 , 20 , 22 , 10 , 11 , 19 , 12 , 16 , 13 , 18 , 15 , 17 , 14 , 00 , 09 , 01 , 07 , 05 , 08 , 03 , 04 , 02 , 06 )
EN_HAD2	enable_had_chan_type := ( 58 , 56 , 61 , 55 , 59 , 52 , 63 , 54 , 62 , 53 , 60 , 57 , 49 , 48 , 47 , 46 , 45 , 44 )
EN_SPR2	enable_spare_chan_type := ( 63 , 58 , 51 , 50 , 61 , 56 )
EN_EG3	enable_em_chan_type := ( 54 , 52 , 51 , 47 , 49 , 44 , 50 , 46 , 45 , 48 , 57 , 60 , 62 , 56 , 63 , 53 , 61 , 58 , 59 , 55 , 21 , 22 , 23 , 20 , 25 , 24 , 27 , 26 , 18 , 19 , 11 , 16 , 08 , 17 , 09 , 10 , 14 , 12 , 13 , 15 )
EN_HAD3	enable_had_chan_type := ( 39 , 38 , 30 , 31 , 37 , 36 , 35 , 29 , 34 , 33 , 32 , 28 , 01 , 05 , 06 , 04 , 07 , 00 )
EN_SPR3	enable_spare_chan_type := ( 02 , 03 , 40 , 41 , 42 , 4 )
EN_EG4	enable_em_chan_type := ( 10 , 18 , 11 , 19 , 13 , 17 , 12 , 16 , 14 , 15 , 00 , 08 , 01 , 09 , 03 , 06 , 02 , 07 , 04 , 05 , 37 , 38 , 36 , 42 , 34 , 43 , 35 , 41 , 40 , 39 , 31 , 27 , 24 , 30 , 25 , 33 , 26 , 29 , 28 , 32 )
EN_HAD4	enable_had_chan_type := ( 61 , 60 , 23 , 22 , 21 , 20 , 54 , 48 , 49 , 55 , 50 , 51 , 58 , 52 , 59 , 53 , 56 , 57 )
NUM_FIB_Em_ETA	integer := 4
	Width (eta) of Proc FPGA Environment area in Em Fibres.
NUM_FIB_Em_PHI	integer := 10
	Height (phi) of Proc FPGA Environment area in Em Fibres.
NUM_FIB_Had_ETA	integer := 3
	Width (eta) ofEN_HAD3 Proc FPGA Environment area in Had Fibres.
NUM_FIB_Had_PHI	integer := 6
	Height (phi) of Proc FPGA Environment area in Had Fibres.
NUM_FIB_SPARE	integer := 8
	No. Spare Fibres.
N_MGT	integer := 64

Types
enable_em_chan_type	( 0 to 39 ) integer
enable_had_chan_type	( 0 to 17 ) integer
enable_spare_chan_type	( 0 to 5 ) integer
mgt_data_in	( N_MGT- 1 downto 0 ) std_logic_vector ( 31 downto 0 )
mgt_data_out	( N_MGT- 1 downto 0 ) std_logic_vector ( 227 downto 0 )
ram_data_in	( N_MGT- 1 downto 0 ) std_logic_vector ( 227 downto 0 )
FibreColumnEm	( NUM_FIB_Em_PHI - 1 downto 0 ) std_logic_vector ( 227 downto 0 )
	This holds all Em data from a column of fibres in phi for 1 Proc FPGA:
FibreAllEm	( NUM_FIB_Em_ETA - 1 downto 0 ) FibreColumnEm
	This holds all data from Em for 1 Proc FPGA:
FibreColumnHad	( NUM_FIB_Had_PHI - 1 downto 0 ) std_logic_vector ( 227 downto 0 )
	This holds all Had data from a column of fibres in phi for 1 Proc FPGA:
FibreAllHad	( NUM_FIB_Had_ETA - 1 downto 0 ) FibreColumnHad
	This holds all data from Had for 1 Proc FPGA:
FibreAllSpare	( NUM_FIB_SPARE - 1 downto 0 ) std_logic_vector ( 227 downto 0 )
	This holds all data from the spare fibres:
SuperCellData	( 19 downto 0 ) SuperCell

Subtypes
SuperCell	std_logic_vector ( 9 downto 0 )

Records
SuperCells

Detailed Description

eFEX data-types and functions

This file/package contains all types, constants, and functions used to interface from/to the eFEX. The following table reports the connection between the hardware and the fw channel number.

FPGA1

FW Ch	MGT Quad	MiniPOD	Type
MGT_00	110	E03	ECal
MGT_01	110	E09	ECal
MGT_02	110	E07	ECal
MGT_03	110	E01	ECal
MGT_04	111	E05	ECal
MGT_05	111	E0A	ECal
MGT_06	111	E08	ECal
MGT_07	111	E04	ECal
MGT_08	112	E06	ECal
MGT_09	112	E02	ECal
MGT_10	112	E13	ECal
MGT_11	112	E17	ECal
MGT_12	113	E15	ECal
MGT_13	113	E19	ECal
MGT_14	113	E1A	ECal
MGT_15	113	E18	ECal
MGT_16	114	E11	ECal
MGT_17	114	E16	ECal
MGT_18	114	E12	ECal
MGT_19	114	E14	ECal
MGT_20	115	E22	ECal
MGT_21	115	E21	ECal
MGT_22	115	E33	ECal
MGT_23	115	E25	ECal
MGT_24	116	E35	ECal
MGT_25	116	E23	ECal
MGT_26	116	E32	ECal
MGT_27	116	E29	ECal
MGT_28	117	E31	ECal
MGT_29	117	E27	ECal
MGT_30	117	E37	ECal
MGT_31	117	E2A	ECal
MGT_32	118	E39	ECal
MGT_33	118	E24	ECal
MGT_34	118	E3A	ECal
MGT_35	118	E26	ECal
MGT_36	119	E38	ECal
MGT_37	119	E36	ECal
MGT_38	119	E28	ECal
MGT_39	119	E34	ECal
MGT_40	211	H09	HCal-
MGT_41	211	H07	HCal
MGT_42	211	H0B	HCal-
MGT_43	211	H0A	HCal-
MGT_44	212	H05	HCal-
MGT_45	212	H03	HCal-
MGT_46	212	H04	HCal-
MGT_47	212	H01	HCal
MGT_48	213	H08	HCal
MGT_49	213	H00	HCal
MGT_50	213	H02	HCal
MGT_51	213	H06	HCal
MGT_52	214
MGT_53	214
MGT_54	214	H13	HCal-
MGT_55	214	H15	HCal-
MGT_56	215	H14	HCal-
MGT_57	215	H11	HCal
MGT_58	215	H10	HCal
MGT_59	215	H12	HCal
MGT_60	216
MGT_61	216
MGT_62	216
MGT_63	216

For FPGA2

FW Ch	MGT Quad	MiniPOD	Type
MGT_00	110	E6A	ECal
MGT_01	110	E68	ECal
MGT_02	110	E62	ECal
MGT_03	110	E64	ECal
MGT_04	111	E63	ECal
MGT_05	111	E66	ECal
MGT_06	111	E61	ECal
MGT_07	111	E67	ECal
MGT_08	112	E65	ECal
MGT_09	112	E69	ECal
MGT_10	112	E7A	ECal
MGT_11	112	E79	ECal
MGT_12	113	E77	ECal
MGT_13	113	E75	ECal
MGT_14	113	E71	ECal
MGT_15	113	E73	ECal
MGT_16	114	E76	ECal
MGT_17	114	E72	ECal
MGT_18	114	E74	ECal
MGT_19	114	E78	ECal
MGT_20	115	E82	ECal
MGT_21	115	E84	ECal
MGT_22	115	E81	ECal
MGT_23	115	E86	ECal
MGT_24	116	E83	ECal
MGT_25	116	E85	ECal
MGT_26	116	E88	ECal
MGT_27	116	E87	ECal
MGT_28	117	E89	ECal
MGT_29	117	E8A	ECal
MGT_30	117	E98	ECal
MGT_31	117	E96	ECal
MGT_32	118	E92	ECal
MGT_33	118	E94	ECal
MGT_34	118	E9A	ECal
MGT_35	118	E97	ECal
MGT_36	119	E99	ECal
MGT_37	119	E91	ECal
MGT_38	119	E95	ECal
MGT_39	119	E93	ECal
MGT_40	213	SP E40	ECal
MGT_41	213	SP E4B	ECal
MGT_42	213	SP E50	ECal
MGT_43	213	SP E5B	ECal
MGT_44	214	H16	HCal
MGT_45	214	H17	HCal
MGT_46	214	H18	HCal
MGT_47	214	H19	HCal-
MGT_48	215	H1A	HCal-
MGT_49	215	H1B	HCal-
MGT_50	215	SPARE
MGT_51	215	SPARE
MGT_52	217	H26	HCal
MGT_53	217	H22	HCal
MGT_54	217	H24	HCal-
MGT_55	217	H28	HCal
MGT_56	218	H2A	HCal-
MGT_57	218	H20	HCal
MGT_58	218	H2B	HCal-
MGT_59	218	H27	HCal
MGT_60	219	H21	HCal
MGT_61	219	H29	HCal-
MGT_62	219	H23	HCal-
MGT_63	219	H25	HCal-

For FPGA3

FW Ch	MGT Quad	MiniPOD	Type
MGT_00	110	H06	HCal
MGT_01	110	H0B	HCal-
MGT_02	110	E30	SPARE-
MGT_03	110	E3B	SPARE-
MGT_04	111	H08	HCal
MGT_05	111	H0A	HCal-
MGT_06	111	H09	HCal-
MGT_07	111	H07	HCal
MGT_08	115	E28	ECal
MGT_09	115	E26	ECal
MGT_10	115	E25	ECal
MGT_11	115	E2A	ECal
MGT_12	116	E23	ECal
MGT_13	116	E22	ECal
MGT_14	116	E24	ECal
MGT_15	116	E21	ECal
MGT_16	117	E29	ECal
MGT_17	117	E27	ECal
MGT_18	117	E32	ECal
MGT_19	117	E31	ECal
MGT_20	118	E37	ECal
MGT_21	118	E3A	ECal
MGT_22	118	E39	ECal
MGT_23	118	E38	ECal
MGT_24	119	E35	ECal
MGT_25	119	E36	ECal
MGT_26	119	E33	ECal
MGT_27	119	E34	ECal
MGT_28	210	H10	HCal
MGT_29	210	H14	HCal-
MGT_30	210	H19	HCal-
MGT_31	210	H18	HCal
MGT_32	211	H11	HCal
MGT_33	211	H12	HCal
MGT_34	211	H13	HCal-
MGT_35	211	H15	HCal-
MGT_36	212	H16	HCal
MGT_37	212	H17	HCal
MGT_38	212	H1A	HCal-
MGT_39	212	H1B	HCal-
MGT_40	214	E6B	SPARE-
MGT_41	214	E60	SPARE-
MGT_42	214	NC	-
MGT_43	214	NC	-
MGT_44	215	E55	ECal
MGT_45	215	E52	ECal
MGT_46	215	E53	ECal
MGT_47	215	E57	ECal
MGT_48	216	E51	ECal
MGT_49	216	E56	ECal
MGT_50	216	E54	ECal
MGT_51	216	E58	ECal
MGT_52	217	E59	ECal
MGT_53	217	E45	ECal
MGT_54	217	E5A	ECal
MGT_55	217	E41	ECal
MGT_56	218	E47	ECal
MGT_57	218	E4A	ECal
MGT_58	218	E43	ECal
MGT_59	218	E42	ECal
MGT_60	219	E49	ECal
MGT_61	219	E44	ECal
MGT_62	219	E48	ECal
MGT_63	219	E46	ECal

For FPGA4

FW Ch	MGT Quad	MiniPOD	Type
MGT_00	110	E6A	ECal
MGT_01	110	E68	ECal
MGT_02	110	E64	ECal
MGT_03	110	E66	ECal
MGT_04	111	E62	ECal
MGT_05	111	E61	ECal
MGT_06	111	E65	ECal
MGT_07	111	E63	ECal
MGT_08	115	E69	ECal
MGT_09	115	E67	ECal
MGT_10	115	E7A	ECal
MGT_11	115	E78	ECal
MGT_12	116	E74	ECal
MGT_13	116	E76	ECal
MGT_14	116	E72	ECal
MGT_15	116	E71	ECal
MGT_16	117	E73	ECal
MGT_17	117	E75	ECal
MGT_18	117	E79	ECal
MGT_19	117	E77	ECal
MGT_20	119	H20	HCal
MGT_21	119	H21	HCal
MGT_22	119	H22	HCal
MGT_23	119	H23	HCal-
MGT_24	210	E48	ECal
MGT_25	210	E46	ECal
MGT_26	210	E44	ECal
MGT_27	210	E49	ECal
MGT_28	211	E42	ECal
MGT_29	211	E43	ECal
MGT_30	211	E47	ECal
MGT_31	211	E4A	ECal
MGT_32	212	E41	ECal
MGT_33	212	E45	ECal
MGT_34	212	E56	ECal
MGT_35	212	E54	ECal
MGT_36	213	E58	ECal
MGT_37	213	E5A	ECal
MGT_38	213	E59	ECal
MGT_39	213	E51	ECal
MGT_40	214	E52	ECal
MGT_41	214	E53	ECal
MGT_42	214	E57	ECal
MGT_43	214	E55	ECal
MGT_44	215	E40 SP	ECal-
MGT_45	215	E4B SP	ECal-
MGT_46	215	E5B SP	ECal-
MGT_47	215	E50 SP	ECal-
MGT_48	216	H1A	HCal-
MGT_49	216	H19	HCal-
MGT_50	216	H17	HCal
MGT_51	216	H16	HCal
MGT_52	217	H14	HCal-
MGT_53	217	H12	HCal
MGT_54	217	H1B	HCal-
MGT_55	217	H18	HCal
MGT_56	218	H11	HCal
MGT_57	218	H10	HCal
MGT_58	218	H15	HCal-
MGT_59	218	H13	HCal-
MGT_60	219	H24	HCal-
MGT_61	219	H25	HCal-
MGT_62	219	E30 SP	ECal-
MGT_63	219	E3B SP	ECal-

Hadronic Mapping

For Hadron mapping we assumed that the channel mapping within one fiber is numbered as follows (eta Left to Right and Phi Bottom Upward):

03	07	11	15
02	06	10	14
01	05	09	13
00	04	08	12

Fibers are numberd as follows:

FPGA1

H05	H0B	H15
H04	H0A	H14
H03	H09	H13
H02	H08	H12
H01	H07	H11
H00	H06	H10

FPGA2

H1B	H25	H2B
H1A	H24	H2A
H19	H23	H29
H18	H22	H28
H17	H21	H27
H16	H20	H26

FPGA3

H0B	H15	H1B
H0A	H14	H1A
H09	H13	H19
H08	H12	H18
H07	H11	H17
H06	H10	H16

FPGA4

H15	H1B	H25
H14	H1A	H24
H13	H19	H23
H12	H18	H22
H11	H17	H21
H10	H16	H20

Only bottom 3 lines are used in phase 1.

Author

Ian Brawn

Mohammed Siyad

Francesco Gonnella

Definition at line 352 of file efex_data_formats.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/efex_data_formats.vhd