RTL Architecture Reference

Processes
PROCESS_47	( STABLE_CLOCK )
PROCESS_48	( STABLE_CLOCK )

Constants
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY/ STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES+ 10

Types
rst_type	( INIT , ASSERT_COMMON_RESET )

Signals
init_wait_count	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
init_wait_done	std_logic := ' 0 '
common_reset_asserted	std_logic := ' 0 '
common_reset_i	std_logic
state	rst_type := INIT

Detailed Description

Definition at line 91 of file mgt_tx_rx_6g4_common_reset.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd