MultiAdder Entity Reference

Multiple Adder: adds many input words in cascade. More...

Inheritance diagram for MultiAdder:

Entities
Behavioral	architecture
	Multiple Adder: adds many input words in cascade. More...

Libraries
IEEE
work

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
DataTypes	Package <DataTypes>

Generics
stage	integer := 4
delay	integer := 0

Ports
CLK	in	std_logic
		200 MHz clock
IN_Words	in	DataWords ( ( 2 ** stage ) - 1 downto 0 )
OUT_Overflow	out	std_logic
OUT_Word	out	DataWord

Detailed Description

Multiple Adder: adds many input words in cascade.

This multi-sage adder works in cascade, adding 2^N numbers together, where N is the number of stages. The minimum latency of the block is N clock cycles (being N the number of stages) A delay might be added to synchronise with outher adders, multipliers, etc.. The total latency is L = N + D clock cycles, where N is the number of stages and D is the delay.

Author

Francesco Gonnella

Definition at line 20 of file MultiAdder.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/MultiAdder.vhd