eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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aurora_hub2 Entity Reference
Inheritance diagram for aurora_hub2:
aurora_reset aurora_wrapper_hub2 efex_aurora_hub2_support efex_aurora_hub2_CLOCK_MODULE efex_aurora_hub2_SUPPORT_RESET_LOGIC efex_aurora_hub2_gt_common_wrapper efex_aurora_hub2_cdc_sync_exdes top_efex_control

Entities

Behavioral  architecture
 

Libraries

IEEE 
infrastructure_lib 

Use Clauses

STD_LOGIC_1164 
NUMERIC_STD 
all  

Ports

s_axi_tx_tdata   in   std_logic_vector ( 63 downto 0 )
s_axi_tx_tvalid   in   std_logic
s_axi_tx_tready   out   std_logic
s_axi_tx_tkeep   in   std_logic_vector ( 7 downto 0 )
s_axi_tx_tlast   in   std_logic
s_axi_ufc_tx_req   in   std_logic
s_axi_ufc_tx_ms   in   std_logic_vector ( 2 downto 0 )
s_axi_ufc_tx_ack   out   std_logic
txp   out   std_logic_vector ( 0 to 3 )
txn   out   std_logic_vector ( 0 to 3 )
gt_refclk1_p   in   std_logic
gt_refclk1_n   in   std_logic
aurora_gt0_txctrl   in   std_logic_vector ( 23 downto 0 )
aurora_gt1_txctrl   in   std_logic_vector ( 23 downto 0 )
aurora_gt2_txctrl   in   std_logic_vector ( 23 downto 0 )
aurora_gt3_txctrl   in   std_logic_vector ( 23 downto 0 )
tx_hard_err   out   std_logic
tx_channel_up   out   std_logic
tx_lane_up   out   std_logic_vector ( 0 to 3 )
user_clk_out   out   std_logic
sys_reset_out   out   std_logic
tx_lock   out   std_logic
init_clk   in   std_logic
init_clk_out   out   std_logic
pll_not_locked   out   std_logic
tx_resetdone   out   std_logic
link_reset   in   std_logic

Detailed Description

Definition at line 29 of file aurora_hub2.vhd.


The documentation for this class was generated from the following file: