RTL Architecture Reference

Processes
PROCESS_27	( init_clk )
PROCESS_28	( init_clk )
PROCESS_29	( init_clk )
PROCESS_30	( init_clk )
PROCESS_31	( init_clk )
PROCESS_32	( init_clk )

Signals
samp1	std_logic := ' 1 '
samp2	std_logic := ' 1 '
btn_samp1	std_logic := ' 0 '
start_seq	std_logic := ' 0 '
count	std_logic_vector ( 15 downto 0 ) := X " 0000 "
pwrcount	std_logic_vector ( 15 downto 0 ) := X " 0000 "
tx_btn_reset	std_logic := ' 0 '
rx_btn_reset	std_logic := ' 0 '
tx_pwr_reset	std_logic := ' 0 '
rx_pwr_reset	std_logic := ' 0 '
rx_pwr_GTReset	std_logic := ' 0 '
tx_pwr_GTReset	std_logic := ' 0 '
rx_btn_GTReset	std_logic := ' 0 '
tx_btn_GTReset	std_logic := ' 0 '
pwr_on	std_logic

Detailed Description

Definition at line 46 of file aurora_reset.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/aurora_reset.vhd